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Georgina Kalogeridou edited this page Aug 27, 2015 · 20 revisions

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Toggle table of contents Pages 63

Home
Acceptance Test Project
Acceptance Test Project Implementation
Acceptance Test Project Vivado 2020.1 and Ubuntu 2020.4
Before opening issues
Contrib. Core: Delay
Contrib. Core: Input Arbiter 6in
Contrib. Core: Large CAM
Contrib. Core: NetFPGA SUME PktGen
Contrib. Core: Rate Limiter
Contrib. Project: Blueswitch
Contrib. Project: Encap Decap
Contrib. Project: Latency Gadget: delay_mb
Contrib. Project: Reference_emu
Contributed Documents
Contributing Code
DDR3 SDRAM Performance with Xilinx MIG
FPGA Programming
Getting Started Guide
Hardware Tests
Hardware Tests Vivado 2020.1 and Ubuntu 2020.4
Installation of Vivado Vitis 2020.1 and 2020.2 on Ubuntu 2020.4 LTS
Known issues
License
Motherboard Information
NetFPGA Design Challenge 2017 Results
NetFPGA SUME Design Flow
NetFPGA SUME FAQ
NetFPGA SUME NetSoC RISCV
NetFPGA SUME Reference Learning Switch
NetFPGA SUME Reference Learning Switch Lite
NetFPGA SUME Reference Learning Switch Lite Vivado 2020.1 and Ubuntu 2020.4
NetFPGA SUME Reference Learning Switch Vivado 2020.1 Ubuntu 2020.4
NetFPGA SUME Reference NIC
NetFPGA SUME Reference NIC Vivado 2020.1 and Ubuntu 2020.4
NetFPGA SUME Reference Router
NetFPGA SUME Reference Router Vivado 2020.4 and Ubuntu 2020.1
NetFPGA SUME Simulations
NetFPGA SUME TCAM IPs
Network Setup for Ubuntu 2020.4 LTS
Projects
Projects Ideas List
Reference NIC iperf tests
Reference Operating System Setup Guide
Reference Operating System Setup Guide (Vivado 2015)
Registers Infrastrcture
Release Notes
Report a security vulnerability
Restore PCIE Configuration
RIFFA DMA Engine
Standard IP Interfaces
Std. Core: 10G Ethernet Interface
Std. Core: 10G Ethernet Interface Shared
Std. Core: Input Arbiter
Std. Core: Output Port Lookup (Learning Switch)
Std. Core: Output Port Lookup (NIC)
Std. Core: Output Port Lookup (Router)
Std. Core: Output Queues
The NetFPGA Contributors
Vivado Licensing
Vlan Adder module
Vlan Remover Module
Xilinx 10G MAC License

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