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Salvator edited this page Dec 12, 2016 · 33 revisions

NetFPGA SUME v1.5.0

This release contains:

  • Updates

    • nf_10ge_attachment_v1_0_0 : Fix the state machine conditions in tx and rx queue modules to revolve the interface stall issues. Fix the reset signal connection in tx and rx queue modules

  • Bug Fix

    • reference_switch_lite : Fix the reset signal which caused negative slack in the reference_switch_lite bitfile
    • axitools.py : Fix a typo, an undefined variable was crashing the script

  • For known issues please visit this wiki page.
    The open issues can also be seen on this link.
    The procedure to open new issue tickets can be viewed [here] (https://github.com/NetFPGA/NetFPGA-SUME-public/wiki/Before-opening-issues).

NetFPGA SUME v1.4.0

This release contains:

  • Contributed Projects

    • reference_nic_nfmac10g : Implementation of the reference_nic based on the open-source 10GbE MAC -- wiki
    • delay_mb : A latency control gadget that provides latency variation and rate control -- wiki
    • reference_emu : Includes 3 designs written in C# and translated to Verilog -- wiki

  • Contributed Cores

    • nfmac_10ge_interface_shared_v1_0_0 : Open-source version of the Xilinx ten_gig_eth_mac
    • nfmac_10ge_interface_v1_0_0 : Open-source version of the Xilinx ten_gig_eth_mac
    • delay_v1_0_0 : FIFO-based module that control latency based on timestamps -- wiki
    • rate_limiter_v1_0_0 : FIFO-based module for pacing of data out of the FIFO -- wiki
    • emu_output_port_lookup_v1_0_0 : Output Port Lookup module that supports the reference_emu project

  • For known issues please visit this wiki page.
    The open issues can also be seen on this link.
    The procedure to open new issue tickets can be viewed [here] (https://github.com/NetFPGA/NetFPGA-SUME-public/wiki/Before-opening-issues).

NetFPGA SUME v1.3.0

This release contains:

  • Projects

    • Reference router

  • Contributed projects

    • BlueSwitch

  • Cores

    • router_output_port_lookup_v1_0_0 : Implmentation of IPv4 Reference Router -- wiki page

  • Contributed cores

    • nf_endianess_manager_v1_0_0 : Data conversion between Little <-> Big endianess
    • nf_sume_blueswitch_v1_0_0 : Switch implementing multi-table, compliant with OpenFlow protocol -- wiki page
    • nf_sume_crossbar_v1_0_0 : Part of the BlueSwitch project -- wiki page

  • Tools

    • Registers generation infrastructure: Updated version 2, support of indirect register access -- wiki page

  • Patch

    • switch_output_port_lookup_v1_0_1 :
      • Fix a typo in cam instantiation
      • Update the implementation run, to more aggressive timing closure mode
      • Add new CAM parameters (ADDR_TYPE, MATCH_ADDR_WIDTH)
    • xparam2regdefines.py : Fix bug which produced multiple hashes

  • Xilinx cores

    • cam_v1_1_0/tcam_v1_1_0 : Add new CAM parameters in the wrappers to support the ADDR_TYPE and MATCH_ADDR_WIDTH

  • For known issues please visit this wiki page.
    The open issues can also be seen on this link.
    The procedure to open new issue tickets can be viewed [here] (https://github.com/NetFPGA/NetFPGA-SUME-public/wiki/Before-opening-issues).

NetFPGA SUME v1.2.0

This release contains:

  • Projects
  • Acceptance Test: Added PCIe ibert test
  • Patch
  • NfSumeTest.py: Added a checkbox in the GUI of the acceptance_test to narrow down USB device listing
  • Bug Fix
  • Fixing a typo error in the Makefile of the acceptance_test project

NetFPGA SUME v1.1.0

This release contains:

  • Projects
  • reference_switch ( uses a CAM based output port lookup) -- wiki page
  • reference_switch_lite ( uses register based output port lookup) -- wiki page
    (Note : The reference_switch_lite was the reference_switch project in release 1.0.0 )
  • Cores
  • cam_v1_0_0 : a CAM core based on Xilinx's xapp1151 core -- wiki page
  • tcam_v1_0_0 : a TCAM core based on Xilinx's xapp1151 core -- wiki page
  • switch_output_port_lookup_v1_0_0: learning switch output port lookup, with CAM based lookup table, with registers
  • Bug Fix
  • Fixing a typo error in multiple cores, where "+ +" appears instead of "+" in various counters.

NetFPGA SUME v1.0.0

This release contains:

  • Projects

    • Acceptance Test
    • Reference NIC
    • Reference Switch

  • Cores

    • axi_sim_transactor_v1_0_0: drives an AXI Stream slave using stimuli from an AXI grammar formatted text file
    • axis_sim_pkg_v1_0_0: stream simulation I/O support package
    • axis_sim_record_v1_0_0: records traffic received from an AXI Stream master to an AXI grammar formatted text file
    • axis_sim_stim_v1_0_0: drives an AXI Stream slave using stimuli from an AXI grammar formatted text file
    • barrier_gluelogic_v1_0_0/ barrier_v1_0_0: aggregates barrier good notifications from individual modules and pushes out a global barrier good notification when all modules are ready
    • fallthrough_small_fifo_v1_0_0: small fifo with fallthrough i.e. data valid when rd is high
    • identifier_v1_0_0: used to identify the bitfile loaded in the FPGA (the time it was created and github version)
    • input_arbiter_v1_0_0: input arbiter with registers
    • nf_10ge_attachment_v1_0_0: clock and data conversion between 10GE port and NetFPGA data path
    • nf_10ge_interface_shared_v1_0_0: 10GE SFP+ interface, contains the shared logic per quad of ports
    • nf_10ge_interface_v1_0_0: 10GE SFP+ interface, without shared logic
    • nf_axis_converter_v1_0_0: convert AXI4-Streams to different data width
    • nf_riffa_dma_v1_0_0: NetFPGA-SUME adapted RIFFA DMA Engine
    • nic_output_port_lookup_v1_0_0: nic output port lookup with registers
    • output_queues_v1_0_0: BRAM output queues with registers
    • switch_lite_output_port_lookup_v1_0_0: learning switch output port lookup, with registers-based lookup table, with registers

  • DMA

    • RIFFA DMA Engine: https://github.com/NetFPGA/NetFPGA-SUME-public/wiki/RIFFA-DMA-Engine Operates over PCIe gen.2 x8
    • SUME-RIFFA DMA driver v1.0.0
    • rwaxi: application for registers access using SUME-RIFFA DMA driver
    • generate_register_read: application for testing a project's registers read access using rwaxi
    • generate_register_write: application for testing a project's registers write access using rwaxi

  • Tools

    • Registers generation infrastructure
    • NFTest: Simulation and hardware test harness
    • pci_rescan_run: PCI bus rescan script, following FPGA reconfiguration
    • load_bitfile: FPGA configuration script
    • interface_reconfig: generate configuration files for hardware tests
    • settings: local machine path and project settings

  • Documentation

  • Contributed documents:

    • SUME VC709 FMC: FMC pinout of NetFPGA SUME vs. Xilinx VC709

  • Contributed cores:

    • nf_sume_sfp_clk_init: Clock init for the SUME SFP clock (SI5324)

  • For known issues please visit the following link:

https://github.com/NetFPGA/NetFPGA-SUME-public/wiki/Known-issues

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