feat(difftest): replace ArchReg and Writeback with PhyRegState

This change refactors Difftest interfaces, replacing the previous
ArchReg and WriteBack with PhyRegState and ArchRenameTable.
Note when PhyReg size equals ArchReg, RenameTable can be skipped.

By default, Difftest still extracts PhyReg and RenameTable into
ArchReg on the hardware side, so that the extra multi-read area
is accounted for within Difftest.

When acceleration is enabled, this extraction is deferred to the
software side, eliminating the extra hardware area overhead.

Author: klin02

src/main/scala/nutcore/RF.scala

@@ -29,6 +29,7 @@ trait HasRegFileParameter {
 class RegFile extends HasRegFileParameter with HasNutCoreParameter {
   val rf = Mem(NRReg, UInt(XLEN.W))
   def read(addr: UInt) : UInt = Mux(addr === 0.U, 0.U, rf(addr))
+  def read_all: Seq[UInt] = Seq(0.U) ++ (1 until NRReg).map { idx => rf(idx) }
   def write(addr: UInt, data: UInt) = { rf(addr) := data(XLEN-1,0) }
 } 
 

src/main/scala/nutcore/backend/ooo/Backend.scala

@@ -640,9 +640,9 @@ class Backend_ooo(implicit val p: NutCoreConfig) extends NutCoreModule with HasR
   BoringUtils.addSource(!io.in(0).valid, "perfCntCondMdpNoInst")
 
   if (!p.FPGAPlatform || p.FPGADifftest) {
-    val difftest = DifftestModule(new DiffArchIntRegState)
-    difftest.coreid := 0.U // TODO
-    difftest.value  := VecInit((0 to NRReg-1).map(i => rf.read(i.U)))
+    val difftest = DifftestModule(new DiffPhyIntRegState(NRReg)) // Size = NRREG, use as ArchIntReg
+    difftest.coreid := 0.U
+    difftest.value := VecInit(rf.read_all)
   }
 
   if (!p.FPGAPlatform || p.FPGADifftest) {

src/main/scala/nutcore/backend/ooo/ROB.scala

@@ -510,12 +510,6 @@ class ROB(implicit val p: NutCoreConfig) extends NutCoreModule with HasInstrType
       difftest_commit.fpwen    := false.B
       difftest_commit.wdest    := io.wb(i).rfDest
       difftest_commit.wpdest   := io.wb(i).rfDest
-
-      val difftest_wb = DifftestModule(new DiffIntWriteback, delay = 1)
-      difftest_wb.coreid := 0.U
-      difftest_wb.valid := io.wb(i).rfWen && io.wb(i).rfDest =/= 0.U
-      difftest_wb.address := io.wb(i).rfDest
-      difftest_wb.data := io.wb(i).rfData
     }
   } else {
     BoringUtils.addSource(retireATerm, "ilaWBUvalid")

src/main/scala/nutcore/backend/seq/ISU.scala

@@ -99,8 +99,8 @@ class ISU(implicit val p: NutCoreConfig) extends NutCoreModule with HasRegFilePa
   BoringUtils.addSource(WireInit(io.out.fire), "perfCntCondISUIssue")
 
   if (!p.FPGAPlatform || p.FPGADifftest) {
-    val difftest = DifftestModule(new DiffArchIntRegState)
-    difftest.coreid := 0.U // TODO
-    difftest.value  := VecInit((0 to NRReg-1).map(i => rf.read(i.U)))
+    val difftest = DifftestModule(new DiffPhyIntRegState(NRReg)) // Size = NRREG, use as ArchIntReg
+    difftest.coreid := 0.U
+    difftest.value := VecInit(rf.read_all)
   }
 }

src/main/scala/nutcore/backend/seq/WBU.scala

@@ -1,17 +1,17 @@
 /**************************************************************************************
 * Copyright (c) 2020 Institute of Computing Technology, CAS
 * Copyright (c) 2020 University of Chinese Academy of Sciences
-* 
+*
 * NutShell is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2. 
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
 * You may obtain a copy of Mulan PSL v2 at:
-*             http://license.coscl.org.cn/MulanPSL2 
-* 
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER 
-* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR 
-* FIT FOR A PARTICULAR PURPOSE.  
+*             http://license.coscl.org.cn/MulanPSL2
+*
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR
+* FIT FOR A PARTICULAR PURPOSE.
 *
-* See the Mulan PSL v2 for more details.  
+* See the Mulan PSL v2 for more details.
 ***************************************************************************************/
 
 package nutcore
@@ -57,12 +57,6 @@ class WBU(implicit val p: NutCoreConfig) extends NutCoreModule{
     difftest_commit.fpwen  := false.B
     difftest_commit.wdest  := io.wb.rfDest
     difftest_commit.wpdest := io.wb.rfDest
-
-    val difftest_wb = DifftestModule(new DiffIntWriteback, delay = 1)
-    difftest_wb.coreid  := 0.U
-    difftest_wb.valid   := io.wb.rfWen && io.wb.rfDest =/= 0.U
-    difftest_wb.address := io.wb.rfDest
-    difftest_wb.data    := io.wb.rfData
   } else {
     BoringUtils.addSource(io.in.valid, "ilaWBUvalid")
     BoringUtils.addSource(io.in.bits.decode.cf.pc, "ilaWBUpc")