V1.3.0

Two new simple socs added for working with the code generated from the RARS simulador:

• soc-rars-MMIO-1-port: One output ports at 0xFFFF0000
• soc-rars-MMIO-2-ports: Two output ports at 0xFFFF0000 and 0xFFFF0010

v1.2.1

Minor update. README updated with a screenshot and an animated gif for showing the demo

v1.2.0

PICOSOC fully migrated to Icestudio, using blocks for the different parts
The Example firmware in C has been simplified

V1.1.0

Verilog files integrates into code blocks
No external verilog files are needed

V1.0.0

Initial release with hello world examples both in c and asm