Fix: Use standard CMSIS constant for SCB SLEEPDEEP register access

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Fix: Use standard CMSIS constant for SCB SLEEPDEEP register access

Description

Addresses review feedback from #148: M33_SCR_SLEEPDEEP_BITS was used without proper definition. Replaced with standard CMSIS constant SCB_SCR_SLEEPDEEP_Msk and SCB->SCR register access.

Changes:

• Added #include <cmsis_core.h> for Cortex-M targets
• Replaced scb_hw->scr with SCB->SCR
• Replaced M33_SCR_SLEEPDEEP_BITS with SCB_SCR_SLEEPDEEP_Msk

// Before
scb_hw->scr |= M33_SCR_SLEEPDEEP_BITS;

// After
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;

This follows the standard pattern used throughout Zephyr for ARM Cortex-M SCB register access.

Related Issues/Tickets

• Addresses feedback from Hibernation Mode #148 (review comment)

How Has This Been Tested?

• Unit tests
• Integration tests
• Z Tests
• Manual testing (describe steps)
  • Code compiles against CMSIS headers
  • Follows established Zephyr patterns (e.g., arch/arm/core/cortex_m/cpu_idle.c)

Screenshots / Recordings (if applicable)

N/A

Checklist

• Written detailed sdd with requirements, channels, ports, commands, telemetry defined and correctly formatted and spelled
• Have written relevant integration tests and have documented them in the sdd
• Have done a code review with
• Have tested this PR on every supported board with correct board definitions

Further Notes / Considerations

This is a stacked PR targeting #148. The CMSIS SCB_SCR_SLEEPDEEP_Msk constant is defined in core_cm33.h and included via cmsis_core.h → cmsis_core_m_defaults.h for RP2350 (Cortex-M33) targets.

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