Fix ctimer PWM 0% duty cycle behavior#540
Merged
jerrysxie merged 3 commits intoOpenDevicePartnership:mainfrom Jan 8, 2026
Merged
Fix ctimer PWM 0% duty cycle behavior#540jerrysxie merged 3 commits intoOpenDevicePartnership:mainfrom
jerrysxie merged 3 commits intoOpenDevicePartnership:mainfrom
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* The length channel match register was off by one, causing 0 duty cycle pwm to have 1 tick of high output instead of always low. * Add example test for 0% and 100% duty cycle behavior using GPIO input monitoring.
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Pull request overview
This pull request fixes an off-by-one error in the CTimer PWM period configuration that caused 0% duty cycle PWM to output one tick of high signal instead of staying always low. The fix adjusts the period match register value to account for zero-based counting.
Key changes:
- Fixed period calculation in
CTimerPwmPeriodChannel::new()by subtracting 1 from period_clock_ticks to properly handle zero-based timer counting - Added PIO0_30 pin support for CTimer match output
- Added example test demonstrating correct 0% and 100% duty cycle behavior using GPIO monitoring
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Copilot reviewed 1 out of 2 changed files in this pull request and generated no comments.
| File | Description |
|---|---|
| src/timer.rs | Fixed off-by-one error in PWM period configuration by subtracting 1 from period_clock_ticks; added PIO0_30 pin support |
| examples/rt685s-evk/src/bin/ctimer-pwm-0-100.rs | New example testing 0% and 100% duty cycle behavior with GPIO input monitoring |
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Pull request overview
Copilot reviewed 1 out of 2 changed files in this pull request and generated no new comments.
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src/timer.rs:1063
- There's an inconsistency between the value written to the hardware register and the value stored in count_max. Line 1057 writes period_clock_ticks - 1 to the hardware (which is correct for the fix), but line 1063 stores the unadjusted period_clock_ticks in count_max. This inconsistency will cause incorrect duty cycle calculations in set_duty and get_duty functions since they use count_max as the scale factor. The count_max should be set to period_clock_ticks - 1 to match what was written to the hardware register.
channel_info.pwm_configure(period_clock_ticks - 1);
Ok(Self {
_lifetime: PhantomData,
period,
clk_freq: clock_rate,
count_max: period_clock_ticks,
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SanjeevKumm
approved these changes
Jan 8, 2026
felipebalbi
approved these changes
Jan 8, 2026
tullom
approved these changes
Jan 8, 2026
sukomath
approved these changes
Jan 8, 2026
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closes #539