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disable fp16 flags on RISC-V unless BUILD_HFLOAT16=1 #5431

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Merged
martin-frbg merged 1 commit into from
Sep 9, 2025
+27 −5
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disable fp16 flags on RISC-V unless BUILD_HFLOAT16=1 #5431

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4 changes: 2 additions & 2 deletions Makefile.prebuild
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Original file line number Diff line number Diff line change
Expand Up @@ -64,11 +64,11 @@ TARGET_FLAGS = -march=rv64imafdcv_zba_zbb_zfh -mabi=lp64d
endif

ifeq ($(TARGET), RISCV64_ZVL256B)
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@markdryan markdryan Aug 28, 2025

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Does anyone see any issue with removing this?

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@martin-frbg martin-frbg Aug 28, 2025

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I don't think you want to remove these entirely, just revert them to their state before the addition of the HFLOAT16 PR (i.e. rv64imafdcv), unless we can be absolutely certain that the getarch utility and everything downstream of c_check still works on any affected RISCV64 platform (I'm especially worried about the -mabi=lp64d part) ?

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@markdryan markdryan Aug 28, 2025

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I was removing these to fix

#5424

but perhaps this is not the way to do this. Perhaps it's best to remove

05c8654

from this PR and fix the issue separately.

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@markdryan markdryan Aug 28, 2025 •
edited
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I've dropped the commit that removes these lines entirely. The remaining commit just removes the half float flags.

TARGET_FLAGS = -march=rv64imafdcv_zvfh_zfh -mabi=lp64d
TARGET_FLAGS = -march=rv64imafdcv -mabi=lp64d
endif

ifeq ($(TARGET), RISCV64_ZVL128B)
TARGET_FLAGS = -march=rv64imafdcv_zvfh_zfh -mabi=lp64d
TARGET_FLAGS = -march=rv64imafdcv -mabi=lp64d
endif

ifeq ($(TARGET), RISCV64_GENERIC)
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12 changes: 11 additions & 1 deletion Makefile.riscv64
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Expand Up @@ -7,12 +7,22 @@ CCOMMON_OPT += -march=rv64imafdcv_zba_zbb_zfh_zvl512b -mabi=lp64d
FCOMMON_OPT += -march=rv64imafdcv_zba_zbb_zfh -mabi=lp64d -static
endif
ifeq ($(CORE), RISCV64_ZVL256B)
ifeq ($(BUILD_HFLOAT16), 1)
CCOMMON_OPT += -march=rv64imafdcv_zvl256b_zvfh_zfh -mabi=lp64d
FCOMMON_OPT += -march=rv64imafdcv_zvfh_zfh -mabi=lp64d
else
CCOMMON_OPT += -march=rv64imafdcv_zvl256b -mabi=lp64d
FCOMMON_OPT += -march=rv64imafdcv -mabi=lp64d
endif
endif
ifeq ($(CORE), RISCV64_ZVL128B)
CCOMMON_OPT += -march=rv64imafdcv_zvfh_zfh -mabi=lp64d
ifeq ($(BUILD_HFLOAT16), 1)
CCOMMON_OPT += -march=rv64imafdcv_zvfh_zfh -mabi=lp64d
FCOMMON_OPT += -march=rv64imafdcv_zvfh_zfh -mabi=lp64d
else
CCOMMON_OPT += -march=rv64imafdcv -mabi=lp64d
FCOMMON_OPT += -march=rv64imafdcv -mabi=lp64d
endif
endif
ifeq ($(CORE), RISCV64_GENERIC)
CCOMMON_OPT += -march=rv64imafdc -mabi=lp64d
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2 changes: 1 addition & 1 deletion driver/others/Makefile
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Expand Up @@ -218,7 +218,7 @@ mulx.$(SUFFIX) : $(ARCH)/mulx.c
$(CC) $(CFLAGS) -c -DXDOUBLE -UCOMPLEX $< -o $(@F)

detect_riscv64.$(SUFFIX): detect_riscv64.c
$(CC) $(CFLAGS) -c -march=rv64imafdcv_zvfh_zfh $< -o $(@F)
$(CC) $(CFLAGS) -c -march=rv64imafdcv $< -o $(@F)

xerbla.$(PSUFFIX) : xerbla.c
$(CC) $(PFLAGS) -c $< -o $(@F)
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14 changes: 13 additions & 1 deletion driver/others/dynamic_riscv64.c
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Expand Up @@ -97,6 +97,8 @@ struct riscv_hwprobe {

#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
#define RISCV_HWPROBE_IMA_V (1 << 2)
#define RISCV_HWPROBE_EXT_ZFH (1 << 27)
#define RISCV_HWPROBE_EXT_ZVFH (1 << 30)

#ifndef NR_riscv_hwprobe
#ifndef NR_arch_specific_syscall
Expand Down Expand Up @@ -147,6 +149,7 @@ char* gotoblas_corename(void) {
}

static gotoblas_t* get_coretype(void) {
uint64_t vector_mask;
unsigned vlenb = 0;

#if !defined(OS_LINUX)
Expand All @@ -165,14 +168,23 @@ static gotoblas_t* get_coretype(void) {
};
int ret = syscall(NR_riscv_hwprobe, pairs, 1, 0, NULL, 0);
if (ret == 0) {
if (!(pairs[0].value & RISCV_HWPROBE_IMA_V))
#if defined(BUILD_HFLOAT16)
vector_mask = (RISCV_HWPROBE_IMA_V | RISCV_HWPROBE_EXT_ZFH | RISCV_HWPROBE_EXT_ZVFH);
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@ChipKerchner ChipKerchner Sep 23, 2025

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Don't you need to check for these also?

#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 28)
#define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31)

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@markdryan markdryan Sep 23, 2025

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Are these extensions being used?

They don't appear to be enabled in the compiler flags

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@ChipKerchner ChipKerchner Sep 23, 2025 •
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__riscv_vle16_v_f16m1 (and other variations) are listed under the Zvfhmin extension. I would think the scalar form is also being used in situations like this _Float16 B0 = B[bi+0];

The ones that you currently have are for the mult and madd instructions.

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@ChipKerchner ChipKerchner Sep 23, 2025

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Ok, I looked it up. Minimum extension is a subset of the regular extension. So what we and you have seem correct.

#else
vector_mask = RISCV_HWPROBE_IMA_V;
#endif
if ((pairs[0].value & vector_mask) != vector_mask)
return NULL;
} else {
#if defined(BUILD_HFLOAT16)
return NULL;
#else
if (!(getauxval(AT_HWCAP) & DETECT_RISCV64_HWCAP_ISA_V))
return NULL;

if (!detect_riscv64_rvv100())
return NULL;
#endif
}

/*
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