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Disable bf16 flags on RISC-V unless BUILD_BFLOAT16=1 #5456

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Merged
martin-frbg merged 3 commits into from
Sep 26, 2025
Merged

Disable bf16 flags on RISC-V unless BUILD_BFLOAT16=1 #5456

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3116749
Disable bf16 flags on RISC-V unless BUILD_BFLOAT16=1
ChipKerchner Sep 23, 2025
9427eaf
Reduce flags for BF16 to only needed ones.
ChipKerchner Sep 23, 2025
fc7d6e6
Change BF16 warning message.
ChipKerchner Sep 23, 2025
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2 changes: 1 addition & 1 deletion Makefile.riscv64
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ ifeq ($(BUILD_HFLOAT16), 1)
RISCV64_OPT := $(RISCV64_OPT)_zvfh_zfh
endif
ifeq ($(BUILD_BFLOAT16), 1)
RISCV64_OPT := $(RISCV64_OPT)_zfbfmin_zvfbfmin_zvfbfwma
RISCV64_OPT := $(RISCV64_OPT)_zvfbfwma
endif
ifeq ($(CORE), RISCV64_ZVL256B)
CCOMMON_OPT += -march=$(RISCV64_OPT)_zvl256b -mabi=lp64d
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7 changes: 7 additions & 0 deletions driver/others/dynamic_riscv64.c
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Expand Up @@ -99,6 +99,7 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_IMA_V (1 << 2)
#define RISCV_HWPROBE_EXT_ZFH (1 << 27)
#define RISCV_HWPROBE_EXT_ZVFH (1 << 30)
#define RISCV_HWPROBE_EXT_ZVFBFWMA (1 << 54)

#ifndef NR_riscv_hwprobe
#ifndef NR_arch_specific_syscall
Expand Down Expand Up @@ -170,6 +171,8 @@ static gotoblas_t* get_coretype(void) {
if (ret == 0) {
#if defined(BUILD_HFLOAT16)
vector_mask = (RISCV_HWPROBE_IMA_V | RISCV_HWPROBE_EXT_ZFH | RISCV_HWPROBE_EXT_ZVFH);
#elif defined(BUILD_BFLOAT16)
vector_mask = (RISCV_HWPROBE_IMA_V | RISCV_HWPROBE_EXT_ZVFBFWMA);
#else
vector_mask = RISCV_HWPROBE_IMA_V;
#endif
Expand All @@ -180,6 +183,10 @@ static gotoblas_t* get_coretype(void) {
snprintf(coremsg, sizeof(coremsg), "Cpu support for Zfh+Zvfh extensions required due to BUILD_HFLOAT16=1\n");
openblas_warning(1, coremsg);
return NULL;
#elif defined(BUILD_BFLOAT16)
snprintf(coremsg, sizeof(coremsg), "Cpu support for Zvfbfwma extensions required due to BUILD_BFLOAT16=1\n");
openblas_warning(1, coremsg);
return NULL;
#else
if (!(getauxval(AT_HWCAP) & DETECT_RISCV64_HWCAP_ISA_V))
return NULL;
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