lcb: Use artificial resource as register class (#464)

kper · web-flow · commit bc93a02652d3 · 2025-08-10T14:53:20.000+02:00
* lcb: Adding conditions for red flags

* lcb: Use artificial resource as register class
diff --git a/vadl/main/vadl/gcb/passes/operands/model/GcbInstructionRegisterFileOperand.java b/vadl/main/vadl/gcb/passes/operands/model/GcbInstructionRegisterFileOperand.java
@@ -19,9 +19,9 @@
 import java.util.List;
 import vadl.gcb.passes.operands.ReferencesFormatField;
 import vadl.viam.Format;
+import vadl.viam.GeneratesRegisterFileName;
 import vadl.viam.RegisterTensor;
 import vadl.viam.graph.dependency.FieldRefNode;
-import vadl.viam.graph.dependency.FuncParamNode;
 import vadl.viam.graph.dependency.ReadArtificialResNode;
 import vadl.viam.graph.dependency.ReadRegTensorNode;
 import vadl.viam.graph.dependency.WriteArtificialResNode;
@@ -33,7 +33,7 @@
 public class GcbInstructionRegisterFileOperand
     extends GcbDefaultInstructionOperand
     implements ReferencesFormatField {
-  private final RegisterTensor registerFile;
+  private final GeneratesRegisterFileName registerFile;
   private final Format.Field formatField;
 
   /**
@@ -42,7 +42,6 @@ public class GcbInstructionRegisterFileOperand
   public GcbInstructionRegisterFileOperand(ReadRegTensorNode node, Format.Field address) {
     super(node, node.regTensor().simpleName(), address.identifier.simpleName());
     this.registerFile = node.regTensor();
-    this.registerFile.ensure(registerFile.isRegisterFile(), "must be registerfile");
     this.formatField = address;
     node.regTensor().ensure(registerFile.isRegisterFile(), "must be registerfile");
   }
@@ -51,10 +50,9 @@ public GcbInstructionRegisterFileOperand(ReadRegTensorNode node, Format.Field ad
    * Constructor.
    */
   public GcbInstructionRegisterFileOperand(ReadArtificialResNode node, Format.Field address) {
-    super(node, node.resourceDefinition().innerResourceRef().simpleName(),
+    super(node, node.resourceDefinition().simpleName(),
         address.identifier.simpleName());
-    this.registerFile = (RegisterTensor) node.resourceDefinition().innerResourceRef();
-    this.registerFile.ensure(registerFile.isRegisterFile(), "must be registerfile");
+    this.registerFile = node.resourceDefinition();
     this.formatField = address;
     node.resourceDefinition().innerResourceRef()
         .ensure(registerFile.isRegisterFile(), "must be registerfile");
@@ -66,7 +64,6 @@ public GcbInstructionRegisterFileOperand(ReadArtificialResNode node, Format.Fiel
   public GcbInstructionRegisterFileOperand(WriteRegTensorNode node, FieldRefNode address) {
     super(node, node.regTensor().simpleName(), address.formatField().identifier.simpleName());
     this.registerFile = node.regTensor();
-    this.registerFile.ensure(registerFile.isRegisterFile(), "must be registerfile");
     this.formatField = address.formatField();
   }
 
@@ -77,27 +74,12 @@ public GcbInstructionRegisterFileOperand(WriteArtificialResNode node, Format.Fie
     super(node, node.resourceDefinition().innerResourceRef().simpleName(),
         address.identifier.simpleName());
     this.registerFile = (RegisterTensor) node.resourceDefinition().innerResourceRef();
-    this.registerFile.ensure(registerFile.isRegisterFile(), "must be registerfile");
     this.formatField = address;
     node.resourceDefinition().innerResourceRef()
         .ensure(registerFile.isRegisterFile(), "must be registerfile");
   }
 
-  /**
-   * Constructor for pseudo instructions. Pseudo instructions will have a {@link ReadRegTensorNode}
-   * or {@link WriteRegTensorNode} because they are constructed over {@link FuncParamNode}.
-   */
-  public GcbInstructionRegisterFileOperand(RegisterTensor registerFile,
-                                           Format.Field field,
-                                           FuncParamNode funcParamNode) {
-    super(funcParamNode, registerFile.simpleName(),
-        funcParamNode.parameter().identifier.simpleName());
-    this.registerFile = registerFile;
-    this.formatField = field;
-    this.registerFile.ensure(registerFile.isRegisterFile(), "must be registerfile");
-  }
-
-  public RegisterTensor registerFile() {
+  public GeneratesRegisterFileName registerFile() {
     return registerFile;
   }
 
diff --git a/vadl/main/vadl/lcb/passes/llvmLowering/domain/selectionDag/LlvmReadResourceFactory.java b/vadl/main/vadl/lcb/passes/llvmLowering/domain/selectionDag/LlvmReadResourceFactory.java
@@ -0,0 +1,48 @@
+// SPDX-FileCopyrightText : © 2025 TU Wien <vadl@tuwien.ac.at>
+// SPDX-License-Identifier: GPL-3.0-or-later
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <https://www.gnu.org/licenses/>.
+
+package vadl.lcb.passes.llvmLowering.domain.selectionDag;
+
+import javax.annotation.Nullable;
+import vadl.error.Diagnostic;
+import vadl.types.DataType;
+import vadl.viam.ArtificialResource;
+import vadl.viam.Counter;
+import vadl.viam.GeneratesRegisterFileName;
+import vadl.viam.RegisterTensor;
+import vadl.viam.graph.dependency.ExpressionNode;
+import vadl.viam.graph.dependency.FieldRefNode;
+
+/**
+ * Factory for creating reading instances.
+ */
+public class LlvmReadResourceFactory {
+  /**
+   * Based on the {@code registerFile} creates a node.
+   */
+  public ExpressionNode create(GeneratesRegisterFileName registerFile,
+                               FieldRefNode address,
+                               DataType type,
+                               @Nullable Counter counter) {
+    if (registerFile instanceof RegisterTensor registerTensor) {
+      return new LlvmReadRegFileNode(registerTensor, address, type, counter);
+    } else if (registerFile instanceof ArtificialResource artificialResource) {
+      return new LlvmReadArtificialResourceNode(artificialResource, address, type);
+    } else {
+      throw Diagnostic.error("Cannot create a llvm type", registerFile.location()).build();
+    }
+  }
+}
diff --git a/vadl/main/vadl/lcb/passes/llvmLowering/strategies/LlvmInstructionLoweringStrategy.java b/vadl/main/vadl/lcb/passes/llvmLowering/strategies/LlvmInstructionLoweringStrategy.java
@@ -90,6 +90,7 @@
 import vadl.viam.graph.dependency.ReadMemNode;
 import vadl.viam.graph.dependency.ReadRegTensorNode;
 import vadl.viam.graph.dependency.ReadResourceNode;
+import vadl.viam.graph.dependency.SelectNode;
 import vadl.viam.graph.dependency.SideEffectNode;
 import vadl.viam.graph.dependency.SignExtendNode;
 import vadl.viam.graph.dependency.WriteMemNode;
@@ -428,7 +429,8 @@ protected boolean hasRedFlags(
         || hasMultipleOutputs(graph)
         || rejectWhenReadingFromMemory(graph)
         || rejectWhenWritingToMemory(graph)
-        || hasUnreplacedBuiltins(graph)) {
+        || hasUnreplacedBuiltins(graph)
+        || hasSelectNodes(graph)) {
       return true;
     }
 
@@ -455,6 +457,13 @@ Here we essentially have X(rd) = X(rn) which creates the pattern:
         .anyMatch(writeResourceNode -> writeResourceNode.value() instanceof ReadResourceNode);
   }
 
+  /**
+   * If there are any {@link SelectNode} in the graph.
+   */
+  private boolean hasSelectNodes(Graph graph) {
+    return graph.getNodes(SelectNode.class).toList().size() == 1;
+  }
+
   /**
    * If there is a {@link BuiltInCall} which is not {@link LlvmNodeLowerable} and thus
    * wasn't replaced.
diff --git a/vadl/main/vadl/lcb/passes/llvmLowering/strategies/instruction/LlvmInstructionLoweringIndirectJumpAndLinkStrategyImpl.java b/vadl/main/vadl/lcb/passes/llvmLowering/strategies/instruction/LlvmInstructionLoweringIndirectJumpAndLinkStrategyImpl.java
@@ -43,6 +43,7 @@
 import vadl.lcb.passes.llvmLowering.domain.selectionDag.LlvmBrindSD;
 import vadl.lcb.passes.llvmLowering.domain.selectionDag.LlvmFieldAccessRefNode;
 import vadl.lcb.passes.llvmLowering.domain.selectionDag.LlvmReadRegFileNode;
+import vadl.lcb.passes.llvmLowering.domain.selectionDag.LlvmReadResourceFactory;
 import vadl.lcb.passes.llvmLowering.domain.selectionDag.LlvmTargetCallSD;
 import vadl.lcb.passes.llvmLowering.strategies.LlvmInstructionLoweringStrategy;
 import vadl.lcb.passes.llvmLowering.tablegen.model.TableGenPattern;
@@ -52,8 +53,8 @@
 import vadl.types.Type;
 import vadl.viam.Abi;
 import vadl.viam.Constant;
+import vadl.viam.GeneratesRegisterFileName;
 import vadl.viam.Instruction;
-import vadl.viam.RegisterTensor;
 import vadl.viam.graph.Graph;
 import vadl.viam.graph.NodeList;
 import vadl.viam.graph.dependency.ConstantNode;
@@ -166,10 +167,13 @@ protected List<TableGenPattern> generatePatternVariations(
     var selector = new Graph("selector");
     var ref = (ReadRegTensorNode) inputRegister.origin().copy();
     var address = (FieldRefNode) ref.address().copy();
-    selector.addWithInputs(new LlvmTargetCallSD(new NodeList<>(new LlvmReadRegFileNode(
-        inputRegister.registerFile(), address, inputRegister.formatField().type(),
-        ref.staticCounterAccess()
-    )),
+    var factory = new LlvmReadResourceFactory();
+    selector.addWithInputs(new LlvmTargetCallSD(
+        new NodeList<>(
+            factory.create(inputRegister.registerFile(), address,
+                inputRegister.formatField().type(),
+                ref.staticCounterAccess())
+        ),
         Type.dummy()));
 
     var database = new Database(supportedInstructions);
@@ -272,7 +276,8 @@ private TableGenPattern generateBranchIndirectWithAdd(
     var selector = new Graph("selector");
     var ref = (ReadRegTensorNode) inputRegister.origin().copy();
     var address = (FieldRefNode) ref.address().copy();
-    var llvmRegister = new LlvmReadRegFileNode(
+    var factory = new LlvmReadResourceFactory();
+    var llvmRegister = factory.create(
         inputRegister.registerFile(), address, inputRegister.formatField().type(),
         ref.staticCounterAccess()
     );
@@ -301,7 +306,8 @@ private TableGenPattern generateBranchIndirectWithZero(
     var selector = new Graph("selector");
     var ref = (ReadRegTensorNode) inputRegister.origin().copy();
     var address = (FieldRefNode) ref.address().copy();
-    var llvmRegister = new LlvmReadRegFileNode(
+    var factory = new LlvmReadResourceFactory();
+    var llvmRegister = factory.create(
         inputRegister.registerFile(), address, inputRegister.formatField().type(),
         ref.staticCounterAccess()
     );
@@ -319,7 +325,7 @@ private TableGenPattern generateBranchIndirectWithZero(
     return new TableGenSelectionWithOutputPattern(selector, machine);
   }
 
-  private static String zeroRegister(RegisterTensor registerFile) {
+  private static String zeroRegister(GeneratesRegisterFileName registerFile) {
     var constraint =
         ensurePresent(
             Arrays.stream(registerFile.constraints()).filter(x -> x.value().intValue() == 0)
@@ -328,6 +334,6 @@ private static String zeroRegister(RegisterTensor registerFile) {
                 registerFile.location())
         );
 
-    return registerFile.simpleName() + constraint.indices().getFirst().intValue();
+    return registerFile.identifier().simpleName() + constraint.indices().getFirst().intValue();
   }
 }
diff --git a/vadl/test/resources/snapshots/aarch64/InstrInfoTableGen.td b/vadl/test/resources/snapshots/aarch64/InstrInfoTableGen.td
