Utage check rtl align

configs/example/idealkmhv3.py

@@ -80,6 +80,7 @@ def setKmhV3IdealParams(args, system):
         if args.bp_type == 'DecoupledBPUWithBTB':
             cpu.branchPred.ftq_size = 64
             cpu.branchPred.fsq_size = 64
+            # cpu.branchPred.microtage.enabled = False
 
         # l1 cache per core
         if args.caches:

configs/example/kmhv3.py

@@ -101,7 +101,7 @@ def setKmhV3Params(args, system):
 
             cpu.branchPred.ubtb.enabled = True
             cpu.branchPred.abtb.enabled = True
-            cpu.branchPred.microtage.enabled = False
+            cpu.branchPred.microtage.enabled = True
             cpu.branchPred.mbtb.enabled = True
             cpu.branchPred.tage.enabled = True
             cpu.branchPred.ittage.enabled = True

src/cpu/pred/BranchPredictor.py

@@ -1060,16 +1060,33 @@ class BTBTAGE(TimedBaseBTBPredictor):
     enableBankConflict = Param.Bool(False, "Enable bank conflict simulation")
     numDelay = 2
 
-class MicroTAGE(BTBTAGE):
-    """A smaller TAGE predictor configuration to assist uBTB"""
-    enableSC = Param.Bool(False, "Enable SC or not")    # TODO: BTBTAGE doesn't support SC
-    numPredictors = 1
-    tableSizes = [512]
-    TTagBitSizes = [16]
-    TTagPcShifts = [1]
+class MicroTAGE(TimedBaseBTBPredictor):
+    """Micro-sized BTB TAGE predictor used alongside uBTB"""
+    type = 'MicroTAGE'
+    cxx_class = 'gem5::branch_prediction::btb_pred::MicroTAGE'
+    cxx_header = "cpu/pred/btb/microtage.hh"
+
+    needMoreHistories = Param.Bool(True, "MicroTAGE needs more histories")
+    enableSC = Param.Bool(False, "Enable SC or not")
+    updateOnRead = Param.Bool(True,"Enable update on read, no need to save tage meta in FTQ")
+    # Keep vector parameters consistent with numPredictors to avoid constructor asserts.
+    numPredictors = Param.Unsigned(4, "Number of TAGE predictors")
+    tableSizes = VectorParam.Unsigned([512] * 4,"the TAGE T0~Tn length")
+    TTagBitSizes = VectorParam.Unsigned([15,15,16,16],"the T0~Tn entry's tag bit size")
+    TTagPcShifts = VectorParam.Unsigned([1] * 4 ,"when the T0~Tn entry's tag generating, PC right shift")
+    blockSize = Param.Unsigned(32,"tage index function uses 32B aligned block address")
 
-    histLengths = [16]
-    numDelay = 0
+    histLengths = VectorParam.Unsigned([5,9,16,24] ,"the BTB TAGE T0~Tn history length")
+    maxHistLen = Param.Unsigned(970,"The length of history passed from DBP")
+    numTablesToAlloc = Param.Unsigned(1,"The number of table to allocated each time")
+    numWays = Param.Unsigned(1, "Number of ways per set")
+    baseTableSize = Param.Unsigned(256,"Base table size")
+    maxBranchPositions = Param.Unsigned(32,"Maximum branch positions per 64-byte block")
+    useAltOnNaSize = Param.Unsigned(128,"Size of the useAltOnNa table")
+    useAltOnNaWidth = Param.Unsigned(7,"Width of the useAltOnNa table")
+    numBanks = Param.Unsigned(4,"Number of banks for bank conflict simulation")
+    enableBankConflict = Param.Bool(False,"Enable bank conflict simulation")
+    numDelay = Param.Unsigned(0,"Prediction latency in cycles")
 
 class BTBITTAGE(TimedBaseBTBPredictor):
     type = 'BTBITTAGE'
@@ -1170,7 +1187,7 @@ class DecoupledBPUWithBTB(BranchPredictor):
     numStages = Param.Unsigned(4, "Maximum number of stages in the pipeline")
     ubtb = Param.UBTB(UBTB(), "UBTB predictor")
     abtb = Param.AheadBTB(AheadBTB(), "ABTB predictor")
-    microtage = Param.BTBTAGE(MicroTAGE(), "MicroTAGE predictor to assist uBTB")
+    microtage = Param.MicroTAGE(MicroTAGE(), "MicroTAGE predictor to assist uBTB")
     mbtb = Param.MBTB(MBTB(), "MBTB predictor")
     tage = Param.BTBTAGE(BTBTAGE(), "TAGE predictor")
     ittage = Param.BTBITTAGE(BTBITTAGE(), "ITTAGE predictor")

src/cpu/pred/SConscript

@@ -49,7 +49,8 @@ SimObject('BranchPredictor.py', sim_objects=[
     'DecoupledStreamBPU', 'DefaultFTB', 'DecoupledBPUWithFTB',
     'TimedBaseFTBPredictor', 'FTBTAGE', 'FTBRAS', 'FTBuRAS', 'FTBITTAGE',
     'AheadBTB', 'MBTB', 'UBTB', 'DecoupledBPUWithBTB',
-    'TimedBaseBTBPredictor', 'BTBRAS', 'BTBTAGE', 'BTBITTAGE', 'BTBMGSC'], enums=["BpType"])
+    'TimedBaseBTBPredictor', 'BTBRAS', 'BTBTAGE', 'MicroTAGE',
+    'BTBITTAGE', 'BTBMGSC'], enums=["BpType"])
 
 DebugFlag('Indirect')
 Source('bpred_unit.cc')
@@ -100,6 +101,7 @@ Source('btb/abtb.cc')
 Source('btb/mbtb.cc')
 Source('btb/timed_base_pred.cc')
 Source('btb/btb_tage.cc')
+Source('btb/microtage.cc')
 Source('btb/btb_ittage.cc')
 Source('btb/btb_mgsc.cc')
 Source('btb/folded_hist.cc')
@@ -125,6 +127,7 @@ DebugFlag('FTB')
 DebugFlag('TAGE')
 DebugFlag('TAGEUseful')
 DebugFlag('TAGEHistory')
+DebugFlag('UTAGE')
 DebugFlag('ITTAGE')
 DebugFlag('ITTAGEHistory')
 DebugFlag('FoldedHist')

src/cpu/pred/btb/decoupled_bpred.hh

@@ -20,6 +20,7 @@
 #include "cpu/pred/btb/btb_tage.hh"
 #include "cpu/pred/btb/btb_ubtb.hh"
 #include "cpu/pred/btb/mbtb.hh"
+#include "cpu/pred/btb/microtage.hh"
 #include "cpu/pred/btb/ras.hh"
 #include "cpu/pred/general_arch_db.hh"
 
@@ -81,7 +82,7 @@ class DecoupledBPUWithBTB : public BPredUnit
     UBTB *ubtb{};
     AheadBTB *abtb{};
     MBTB *mbtb{};
-    BTBTAGE *microtage{};
+    MicroTAGE *microtage{};
     BTBTAGE *tage{};
     BTBITTAGE *ittage{};
     BTBMGSC *mgsc{};