Bump coupledL2 upstream at Mar 5, 2026

Merge coupledL2 commits from 95e8de to 727a04c (xs/master),
which is the latest on xs/master as of Mar 5, 2026.

Squashed commit of the following:

commit 62195c6
Author: zhanglinjuan <zhanglinjuan16@mails.ucas.ac.cn>
Date:   Mon Dec 01 17:59:00 2025 +0800

    timing(MainPipe): fix critical path from Dir error to GrantBuffer (OpenXiangShan#448)

commit fffb491
Author: Ding Haonan <kumonda@kucro3.org>
Date:   Thu Dec 04 11:36:48 2025 +0800

    timing(TL2CHICoupledL2): 2-stage cap P-Credit Queue (OpenXiangShan#449)

commit f118bca
Author: Yanqin Li <maxpicca@qq.com>
Date:   Tue Dec 16 21:26:05 2025 +0800

    refactor: refine prefetch statistics in topdown monitor (OpenXiangShan#452)

commit b40da89
Author: Ma-YX <71326427+Ma-YX@users.noreply.github.com>
Date:   Wed Dec 17 18:58:51 2025 +0800

    fix(TXDAT): fix wrong DataCheck generation when data invalid (OpenXiangShan#455)

commit e4fd161
Author: Ma-YX <71326427+Ma-YX@users.noreply.github.com>
Date:   Wed Dec 17 21:36:01 2025 +0800

    fix(CoupledL2): fix l2MissMatch io compilation error (OpenXiangShan#456)

commit 4e4a6aa
Author: Kunlin You <youkunlin20@mails.ucas.ac.cn>
Date:   Thu Dec 18 19:13:20 2025 +0800

    feat(clockGate): support disable ClockGate with parameters (OpenXiangShan#451)

commit feacfb5
Author: zhaohong1988 <156632870+zhaohong1988@users.noreply.github.com>
Date:   Fri Dec 19 00:24:20 2025 +0800

    fix(MMIOBridge): modify TIMERRange from fix value to soc parameter (OpenXiangShan#453)

commit c5ad8f4
Author: Yanqin Li <maxpicca@qq.com>
Date:   Fri Dec 19 00:24:53 2025 +0800

    ci: add submodule check and remove the dependency of utility in OpenLLC (OpenXiangShan#454)

commit ea0c313
Author: Ding Haonan <kumonda@kucro3.org>
Date:   Fri Dec 26 09:41:32 2025 +0800

    fix(MMIOBridge): remove redundant BEU range exclusion in L2 (OpenXiangShan#457)

commit f292774
Author: Ding Haonan <kumonda@kucro3.org>
Date:   Thu Jan 08 10:15:15 2026 +0800

    fix(Opcode): missing SnpPreferUniqueFwd in SnpXFwd (OpenXiangShan#460)

commit 59f3025
Author: Ma-YX <71326427+Ma-YX@users.noreply.github.com>
Date:   Wed Jan 14 15:59:43 2026 +0800

    fix(MainPipe): fix l2Error_s3 generation logic (OpenXiangShan#463)

commit 3c9525f
Author: Haoyuan Feng <fenghaoyuan19@mails.ucas.ac.cn>
Date:   Mon Feb 02 10:17:49 2026 +0800

    fix(ClockGate): fix bug that ICG is invalid when disable mbist (OpenXiangShan#470)

commit 0d20557
Author: yulightenyu <145419941+yulightenyu@users.noreply.github.com>
Date:   Tue Mar 03 14:26:16 2026 +0800

    fix(AsyncBridge): restore performance considering async depth is 4 (OpenXiangShan#472)

commit ef2deb5
Author: Ding Haonan <kumonda@kucro3.org>
Date:   Wed Mar 04 16:20:19 2026 +0800

    fix(MSHR): hold LikelyShared on retried writes (OpenXiangShan#474)

commit 727a04c
Author: Haoyuan Feng <fenghaoyuan19@mails.ucas.ac.cn>
Date:   Wed Mar 04 17:01:33 2026 +0800

    feat(mmioBridge): increase mmioBridgeSize to 16 for better NC perf (OpenXiangShan#475)

Author: yu-yake2002

.github/workflows/main.yml

@@ -15,6 +15,23 @@ on:
 
 # A workflow run is made up of one or more jobs that can run sequentially or in parallel
 jobs:
+  check-submodules:
+    runs-on: ubuntu-22.04
+    continue-on-error: false
+    timeout-minutes: 5
+    name: Check Submodules
+    steps:
+      - uses: actions/checkout@v4
+        with:
+          submodules: 'true'
+          fetch-depth: '0'
+      - name: check rocket-chip
+        run: cd rocket-chip && git fetch --all && git merge-base --is-ancestor `git rev-parse HEAD` origin/master
+      - name: check HuanCun
+        run: cd HuanCun && git fetch --all && git merge-base --is-ancestor `git rev-parse HEAD` origin/master
+      - name: check utility
+        run: cd utility && git fetch --all && git merge-base --is-ancestor `git rev-parse HEAD` origin/master
+
   # This workflow contains a single job called "build"
   tl-test_L2:
     # The type of runner that the job will run on
@@ -78,6 +95,7 @@ jobs:
             git clone https://github.com/OpenXiangShan/OpenLLC
             cd OpenLLC && make init
             rm -rf ./coupledL2 && ln -s ../../.. ./coupledL2
+            rm -rf ./utility && ln -s ../../../utility ./utility
             cd ../..
             make openLLC-test-l2l3l2 run THREADS_BUILD=4 CXX_COMPILER=clang++-17
             rm -rf run/*.vcd run/*.fst run/*.log run/*.db

src/main/scala/coupledL2/BaseSlice.scala

@@ -34,13 +34,17 @@ abstract class BaseSliceIO[T_OUT <: BaseOuterBundle](implicit p: Parameters) ext
   val matrixDataOut = DecoupledIO(new MatrixDataBundle())
   val l1Hint = DecoupledIO(new L2ToL1Hint())
   val prefetch = prefetchOpt.map(_ => Flipped(new PrefetchIO))
-  // val msStatus = topDownOpt.map(_ => Vec(mshrsAll, ValidIO(new MSHRStatus)))
   val dirResult = topDownOpt.map(_ => ValidIO(new DirResult))
-  val latePF = topDownOpt.map(_ => ValidIO(UInt(PfSource.pfSourceBits.W)))
+  val hitPfInMSHR = topDownOpt.map(_ => ValidIO(UInt(PfSource.pfSourceBits.W)))
+  val pfSent = topDownOpt.map(_ => ValidIO(UInt(MemReqSource.reqSourceBits.W)))
+  val pfLateInMSHR = topDownOpt.map(_ => ValidIO((UInt(MemReqSource.reqSourceBits.W))))
   val error = DecoupledIO(new L2CacheErrorInfo())
   val l2Miss = Output(Bool())
   val l2Flush = Option.when(cacheParams.enableL2Flush) (Input(Bool()))
   val l2FlushDone = Option.when(cacheParams.enableL2Flush) (Output(Bool()))
+  // statistics
+  val msStatus = topDownOpt.map(_ => Vec(mshrsAll, ValidIO(new MSHRStatus)))
+  val msAlloc = topDownOpt.map(_ => Vec(mshrsAll, ValidIO(new MSHRAllocStatus)))
 }
 
 abstract class BaseSlice[T_OUT <: BaseOuterBundle](implicit p: Parameters) extends L2Module with HasPerfEvents {

src/main/scala/coupledL2/Common.scala

@@ -225,6 +225,48 @@ class PipeEntranceStatus(implicit p: Parameters) extends L2Bundle {
   def g_set = sets(3)
 }
 
+/* MSHR info */
+
+// MSHR exposes signals about allocation to Topdown
+class MSHRAllocStatus()(implicit p: Parameters) extends L2Bundle with HasTLChannelBits{
+  val is_miss = Bool()
+  val is_prefetch = Bool()
+}
+
+// MSHR exposes signals to MSHRCtl and Topdown
+class MSHRStatus(implicit p: Parameters) extends L2Bundle
+  with HasTLChannelBits
+  with HasCHIChannelBits
+{
+  val set         = UInt(setBits.W)
+  val reqTag      = UInt(tagBits.W)
+  val metaTag     = UInt(tagBits.W)
+  val expectProbeAck = Bool()
+  val w_c_resp = Bool()
+  val w_d_resp = Bool()
+  val will_free = Bool()
+
+  /*
+  val way = UInt(wayBits.W)
+  val off = UInt(offsetBits.W)
+  val opcode = UInt(3.W)
+  val param = UInt(3.W)
+  val size = UInt(msgSizeBits.W)
+  val source = UInt(sourceIdBits.W)
+  val alias = aliasBitsOpt.map(_ => UInt(aliasBitsOpt.get.W))
+  val aliasTask = aliasBitsOpt.map(_ => Bool())
+  val needProbeAckData = Bool() // only for B reqs
+  val fromL2pft = prefetchOpt.map(_ => Bool())
+  val needHint = prefetchOpt.map(_ => Bool())
+  */
+
+  // for TopDown usage
+  val reqSource = UInt(MemReqSource.reqSourceBits.W)
+  val is_miss = Bool()
+  val is_prefetch = Bool()
+
+}
+
 // MSHR Task that MainPipe sends to MSHRCtl
 class MSHRRequest(implicit p: Parameters) extends L2Bundle {
   val dirResult = new DirResult()

src/main/scala/coupledL2/CoupledL2.scala

@@ -39,8 +39,9 @@ trait HasCoupledL2Parameters {
   val p: Parameters
   // val tl2tlParams: HasTLL2Parameters = p(L2ParamKey)
   def enableCHI = p(EnableCHI)
+  def enableClockGate = p(EnableL2ClockGate)
   def cacheParams = p(L2ParamKey)
-  def EnablePrivateClint = cacheParams.EnablePrivateClint
+  def PrivateClintRange = cacheParams.PrivateClintRange
 
   def XLEN = 64
   def blocks = cacheParams.sets * cacheParams.ways
@@ -574,18 +575,13 @@ abstract class CoupledL2Base(implicit p: Parameters) extends LazyModule with Has
     })))
     topDown match {
       case Some(t) =>
-        t.io.msStatus.zip(slices).foreach {
-          case (in, s) =>
-            s match {
-              case slice: tl2tl.Slice => in := slice.io_msStatus.get
-              case slice: tl2chi.Slice => in := slice.io_msStatus.get
-            }
-        }
-        t.io.dirResult.zip(slices).foreach {
-          case (res, s) => res := s.io.dirResult.get
-        }
-        t.io.latePF.zip(slices).foreach {
-          case (in, s) => in := s.io.latePF.get
+        for ((s, i) <- slices.zipWithIndex) {
+          t.io.msStatus(i) := s.io.msStatus.get
+          t.io.msAlloc(i) := s.io.msAlloc.get
+          t.io.dirResult(i) := s.io.dirResult.get
+          t.io.hitPfInMSHR(i) := s.io.hitPfInMSHR.get
+          t.io.pfLateInMSHR(i) := s.io.pfLateInMSHR.get
+          t.io.pfSent(i) := s.io.pfSent.get
         }
         t.io.debugTopDown <> io.debugTopDown
       case None => io.debugTopDown.l2MissMatch := false.B

src/main/scala/coupledL2/DataStorage.scala

@@ -75,7 +75,8 @@ class DataStorage(implicit p: Parameters) extends L2Module {
     readMCP2 = true,
     hasMbist = p(L2ParamKey).hasMbist,
     hasSramCtl = p(L2ParamKey).hasSramCtl,
-    extraHold = true
+    extraHold = true,
+    withClockGate = true
   ))
   array.io_en := io.en
   private val mbistPl = MbistPipeline.PlaceMbistPipeline(1, "L2DataStorage", p(L2ParamKey).hasMbist)

src/main/scala/coupledL2/L2Param.scala

@@ -19,15 +19,16 @@ package coupledL2
 
 import chisel3._
 import chisel3.util.log2Ceil
-import freechips.rocketchip.diplomacy.{BufferParams, AddressSet}
+import freechips.rocketchip.diplomacy.{AddressSet, BufferParams}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
 import org.chipsalliance.cde.config.Field
 import huancun.{AliasKey, CacheParameters, IsHitKey, PrefetchKey}
 import coupledL2.prefetch._
-import utility.{MemReqSource, ReqSourceKey, Code}
+import utility.{Code, MemReqSource, ReqSourceKey}
 
 case object EnableCHI extends Field[Boolean](false)
+case object EnableL2ClockGate extends Field[Boolean](true)
 
 // L1 Cache Params, used for TestTop generation
 case class L1Param
@@ -91,7 +92,7 @@ case class L2Param(
    * 2 for all except prefetch & !accessed
    * 3 for all
    */
-  mmioBridgeSize: Int = 8,
+  mmioBridgeSize: Int = 16,
 
   // Client
   echoField: Seq[BundleFieldBase] = Nil,
@@ -115,6 +116,8 @@ case class L2Param(
   prefetch: Seq[PrefetchParameters] = Nil,
   // L2 Flush
   enableL2Flush: Boolean = false,
+  // AsyncBridge
+  enableCHIAsyncBridge: Option[Boolean] = None,
   // Performance analysis
   enablePerf: Boolean = true,
   // RollingDB
@@ -147,8 +150,8 @@ case class L2Param(
   hasMbist: Boolean = false,
   hasSramCtl: Boolean = false,
 
-  // Enable new clint
-  EnablePrivateClint: Boolean = false
+  // both EnablePrivateClint and PrivateClintRange are from soc parameters.
+  PrivateClintRange: Option[AddressSet] = None
 ) {
   def toCacheParams: CacheParameters = CacheParameters(
     name = name,

src/main/scala/coupledL2/RequestBuffer.scala

@@ -87,7 +87,8 @@ class RequestBuffer(flow: Boolean = true, entries: Int = 4)(implicit p: Paramete
       val set = UInt(setBits.W)
     }))
 
-    val hasLatePF = ValidIO(UInt(PfSource.pfSourceBits.W))
+    val hasHitPfInMSHR = ValidIO(UInt(PfSource.pfSourceBits.W))
+    val hasPfLateInMSHR = ValidIO(UInt(MemReqSource.reqSourceBits.W))
     val hasMergeA = Output(Bool())
   })
 
@@ -177,10 +178,6 @@ class RequestBuffer(flow: Boolean = true, entries: Int = 4)(implicit p: Paramete
   val canFlow =flow.B && !full && !conflict(in) && !chosenQValid && !Cat(io.mainPipeBlock).orR && !noFreeWay(in)
 
   val doFlow  = canFlow && io.out.ready
-  val latePrefetchRes = latePrefetch(in)
-  io.hasLatePF.valid := latePrefetchRes._1 && io.in.valid && !sameAddr(in, RegNext(in))
-  io.hasLatePF.bits := latePrefetchRes._2
-  io.hasMergeA := mergeA && io.in.valid && !sameAddr(in, RegNext(in))
 
   //  val depMask    = buffer.map(e => e.valid && sameAddr(io.in.bits, e.task))
   // remove duplicate prefetch if same-addr A req in MSHR or ReqBuf
@@ -194,6 +191,14 @@ class RequestBuffer(flow: Boolean = true, entries: Int = 4)(implicit p: Paramete
   ).asUInt
   val dup        = isPrefetch && dupMask.orR
 
+  // statistics io
+  val latePrefetchRes = latePrefetch(in)
+  io.hasHitPfInMSHR.valid := latePrefetchRes._1 && io.in.valid && !sameAddr(in, RegNext(in))
+  io.hasHitPfInMSHR.bits := latePrefetchRes._2
+  io.hasPfLateInMSHR.valid := io.in.valid && dup
+  io.hasPfLateInMSHR.bits := io.in.bits.reqSource
+  io.hasMergeA := mergeA && io.in.valid && !sameAddr(in, RegNext(in))
+
   //!! TODO: we can also remove those that duplicate with mainPipe
 
   /* ======== Alloc ======== */