feat(Xstatistics): powerful perf counter

src/main/scala/utility/ChiselTaggedTrace.scala

@@ -24,7 +24,19 @@ import freechips.rocketchip.amba.ahb.AHBImpMaster.bundle
 
 trait HasDPICUtils extends BlackBox with HasBlackBoxInline {
   var moduleName: String = ""
-  def init(args: Bundle, negedge: Boolean = false, comb_output: Boolean = false) = {
+
+  /**
+    *
+    * make module that call dpic function
+    * 
+    * io must contains "clock, reset, en"
+    *
+    * @param args input the io
+    * @param negedge trigger on negedge clock
+    * @param comb_output if has output, use wire out not reg
+    * @param overrideFuncname override the dpic name, default is class name
+    */
+  def init(args: Bundle, negedge: Boolean = false, comb_output: Boolean = false, overrideFuncname: String = "") {
     val field = args.elements.map(t => {
       val name = t._1
       val tpes = t._2.getClass.getMethods.map(x => x.getName()).toList
@@ -48,9 +60,9 @@ trait HasDPICUtils extends BlackBox with HasBlackBoxInline {
       throw new Exception
     }
 
-    val className = this.getClass().getSimpleName()
-    moduleName = className + "_DPIC_Helper"
-    val dpicFunc = lang.Character.toLowerCase(className.charAt(0)) + className.substring(1)
+    val dpic_name = if (overrideFuncname.isEmpty()) this.getClass().getSimpleName() else overrideFuncname
+    moduleName = dpic_name + "_DPIC_Helper"
+    val dpicFunc = lang.Character.toLowerCase(dpic_name.charAt(0)) + dpic_name.substring(1)
     val verilog =
       s"""
          |import "DPI-C" function ${if (has_out) "longint unsigned" else "void"} $dpicFunc

src/main/scala/utility/LogUtils.scala

@@ -77,6 +77,7 @@ private[utility] trait XSLogTap {
 object XSLog extends XSLogTap {
   private val logInfos = ListBuffer.empty[LogPerfParam]
   private val callBacks = ListBuffer.empty[(LogPerfIO) => Unit]
+  private val callBacksWithClock = ListBuffer.empty[(LogPerfIO, Reset, Clock) => Unit]
   private val logModules = ListBuffer.empty[BaseModule]
 
   private def unpackPrintable(pable: Printable): (String, Seq[Data]) = {
@@ -158,7 +159,9 @@ object XSLog extends XSLogTap {
   // As XSPerf depends on LogPerfIO, their apply will be buffered until collection
   // Register collect() method from Callers when first apply, then call that during collection
   def registerCaller(caller: LogPerfIO => Unit): Unit = callBacks += caller
+  def registerCallerWithClock(caller: (LogPerfIO, Reset, Clock) => Unit): Unit = callBacksWithClock += caller
   def invokeCaller(ctrl: LogPerfIO): Unit = callBacks.foreach(caller => caller(ctrl))
+  def invokeCallerWithClock(ctrl: LogPerfIO, reset: Reset, clock: Clock) = callBacksWithClock.foreach(caller => caller(ctrl, reset, clock))
 
   // Should only be called during firrtl phase(ChiselStage)
   // PathName can not be accessed until circuit elaboration
@@ -205,6 +208,7 @@ private class LogPerfEndpoint()(implicit p: Parameters) extends Module {
   }
 
   // To collect deferred call from XSPerf/..., invoke all registered caller
+  XSLog.invokeCallerWithClock(io, reset, clock)
   XSLog.invokeCaller(io)
   // Group printfs with same cond to reduce system tasks for better thread schedule
   XSLog.tapInfos.groupBy(_.cond).values.foreach { infos =>

src/main/scala/utility/PerfCounterUtils.scala

@@ -75,7 +75,6 @@ object XSPerfAccumulate extends HasRegularPerfName with XSLogTap {
       val next_counter = WireInit(0.U(64.W)).suggestName(perfName + "Next")
       next_counter := counter + perfCnt
       counter := Mux(perfClean, 0.U, next_counter)
-
       XSPerfPrint(curMod)(perfDump, p"$perfName, $next_counter\n")
     }
   }