feat(difftest): replace ArchReg and Writeback with PhyRegState

This change refactors Difftest interfaces, replacing the previous
ArchReg and WriteBack with PhyRegState and ArchRenameTable.

By default, Difftest still extracts PhyReg and RenameTable into
ArchReg on the hardware side, so that the extra multi-read area
is accounted for within Difftest.

When acceleration is enabled, this extraction is deferred to the
software side, eliminating the extra hardware area overhead.

Since 128-bit ArchVecReg are now treated as two 64-bit registers
in Difftest, we add corresponding register splitting in XiangShan.
The address indexs (InstrCommit.otherwpdest and RenameTable) are
also converted from `index` to `2*index` and `2*index + 1` for reg
splitting.

Note XiangShan separates V0 and Vf register files. When mering the
two regfiles and renameTable for Difftest, the indexs of Vf must
add offset of V0RegSize to ensure correct indexing.

Author: klin02

src/main/scala/xiangshan/backend/Backend.scala

@@ -369,10 +369,6 @@ class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parame
   // for fpIQ write int regfile arbiter
   intRegion.io.fromFpIQ.get <> fpRegion.io.fpIQOut.get
 
-  intRegion.io.diffIntRat.foreach(_ := ctrlBlock.io.diff_int_rat.get)
-  fpRegion.io.diffFpRat.foreach(_ := ctrlBlock.io.diff_fp_rat.get)
-  vecRegion.io.diffVecRat.foreach(_ := ctrlBlock.io.diff_vec_rat.get)
-  vecRegion.io.diffV0Rat.foreach(_ := ctrlBlock.io.diff_v0_rat.get)
   vecRegion.io.diffVlRat.foreach(_ := ctrlBlock.io.diff_vl_rat.get)
   vecRegion.io.fromVecExcpMod.get.r := vecExcpMod.o.toVPRF.r
   vecRegion.io.fromVecExcpMod.get.w := vecExcpMod.o.toVPRF.w

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -649,6 +649,7 @@ class CtrlBlockImp(
   memCtrl.io.mdpFlodPcVec := mdpFlodPcVec
   memCtrl.io.dispatchLFSTio <> dispatch.io.lfst
 
+  rat.io.hartId := io.fromTop.hartId
   rat.io.redirect := s1_s3_redirect.valid
   rat.io.rabCommits := rob.io.rabCommits
   rat.io.diffCommits.foreach(_ := rob.io.diffCommits.get)
@@ -809,10 +810,6 @@ class CtrlBlockImp(
   // rob to mem block
   io.robio.lsq <> rob.io.lsq
 
-  io.diff_int_rat.foreach(_ := rat.io.diff_int_rat.get)
-  io.diff_fp_rat .foreach(_ := rat.io.diff_fp_rat.get)
-  io.diff_vec_rat.foreach(_ := rat.io.diff_vec_rat.get)
-  io.diff_v0_rat .foreach(_ := rat.io.diff_v0_rat.get)
   io.diff_vl_rat .foreach(_ := rat.io.diff_vl_rat.get)
 
   rob.io.debug_ls := io.robio.debug_ls
@@ -1006,10 +1003,6 @@ class CtrlBlockIO()(implicit p: Parameters, params: BackendParams) extends XSBun
       val lsdqFull  = Bool()
     }
   })
-  val diff_int_rat = if (params.basicDebugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None
-  val diff_fp_rat  = if (params.basicDebugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None
-  val diff_vec_rat = if (params.basicDebugEn) Some(Vec(31, Output(UInt(PhyRegIdxWidth.W)))) else None
-  val diff_v0_rat  = if (params.basicDebugEn) Some(Vec(1, Output(UInt(PhyRegIdxWidth.W)))) else None
   val diff_vl_rat  = if (params.basicDebugEn) Some(Vec(1, Output(UInt(PhyRegIdxWidth.W)))) else None
 
   val sqCanAccept = Input(Bool())

src/main/scala/xiangshan/backend/Region.scala

@@ -533,7 +533,6 @@ class Region(val params: SchdBlockParams)(implicit p: Parameters) extends XSModu
     dataPath.io.fromIntWb := wbDataPath.io.toIntPreg
     dataPath.io.fromPcTargetMem <> io.fromPcTargetMem.get
     dataPath.io.fromBypassNetwork := bypassNetwork.io.toDataPath
-    dataPath.io.diffIntRat.foreach(_ := io.diffIntRat.get)
 
     bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu
     bypassNetwork.io.fromDataPath.immInfo := dataPath.io.og1ImmInfo
@@ -656,7 +655,6 @@ class Region(val params: SchdBlockParams)(implicit p: Parameters) extends XSModu
     io.fpToIntIQResp.get := dataPath.io.toIntIQ
     dataPath.io.fromFpWb := wbDataPath.io.toFpPreg
     dataPath.io.fromBypassNetwork <> bypassNetwork.io.toDataPath
-    dataPath.io.diffFpRat.foreach(_ := io.diffFpRat.get)
     io.toFpPreg := wbDataPath.io.toFpPreg
     bypassNetwork.io.fromDataPath.fp <> dataPath.io.toFpExu
 
@@ -774,8 +772,6 @@ class Region(val params: SchdBlockParams)(implicit p: Parameters) extends XSModu
     dataPath.io.fromV0Wb := wbDataPath.io.toV0Preg
     dataPath.io.fromVlWb := wbDataPath.io.toVlPreg
     dataPath.io.fromBypassNetwork <> bypassNetwork.io.toDataPath
-    dataPath.io.diffVecRat.foreach(_ := io.diffVecRat.get)
-    dataPath.io.diffV0Rat.foreach(_ := io.diffV0Rat.get)
     dataPath.io.diffVlRat.foreach(_ := io.diffVlRat.get)
 
     dataPath.io.fromVecExcpMod.foreach(_ := io.fromVecExcpMod.get)
@@ -995,10 +991,6 @@ class RegionIO(val params: SchdBlockParams)(implicit p: Parameters) extends XSBu
   val flush = Flipped(ValidIO(new Redirect))
   val ldCancel = Vec(backendParams.LduCnt, Flipped(new LoadCancelIO))
   val fromPcTargetMem = Option.when(params.isIntSchd)(Flipped(new PcToDataPathIO(backendParams)))
-  val diffIntRat = Option.when(params.isIntSchd)(Input(Vec(32, UInt(params.pregIdxWidth.W))))
-  val diffFpRat = Option.when(params.isFpSchd)(Input(Vec(32, UInt(params.pregIdxWidth.W))))
-  val diffVecRat = Option.when(params.isVecSchd)(Input(Vec(31, UInt(params.pregIdxWidth.W))))
-  val diffV0Rat = Option.when(params.isVecSchd)(Input(Vec(1, UInt(log2Up(V0PhyRegs).W))))
   val diffVlRat = Option.when(params.isVecSchd)(Input(Vec(1, UInt(log2Up(VlPhyRegs).W))))
   val diffVl = Option.when(params.isVecSchd)(Output(UInt(VlData().dataWidth.W)))
   val vlWriteBackInfoIn = new Bundle {

src/main/scala/xiangshan/backend/datapath/DataPath.scala

@@ -3,7 +3,7 @@ package xiangshan.backend.datapath
 import org.chipsalliance.cde.config.Parameters
 import chisel3._
 import chisel3.util._
-import difftest.{DiffArchFpRegState, DiffArchIntRegState, DiffArchVecRegState, DifftestModule}
+import difftest._
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import utility._
 import utils.SeqUtils._
@@ -265,38 +265,29 @@ class DataPath(implicit p: Parameters, params: BackendParams, param: SchdBlockPa
   io.fromPcTargetMem.fromDataPathFtqPtr := pcReadFtqPtr
   io.fromPcTargetMem.fromDataPathFtqOffset := pcReadFtqOffset
 
-  private val intDiffRead: Option[(Vec[UInt], Vec[UInt])] =
-    OptionWrapper(backendParams.basicDebugEn && param.isIntSchd, (Wire(Vec(32, UInt(intSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W)))))
-  private val fpDiffRead: Option[(Vec[UInt], Vec[UInt])] =
-    OptionWrapper(backendParams.basicDebugEn && param.isFpSchd, (Wire(Vec(32, UInt(fpSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W)))))
-  private val vfDiffRead: Option[(Vec[UInt], Vec[UInt])] =
-    OptionWrapper(backendParams.basicDebugEn && param.isVecSchd, (Wire(Vec(31, UInt(vecSchdParams.pregIdxWidth.W))), Wire(Vec(31, UInt(VLEN.W)))))
-  private val v0DiffRead: Option[(Vec[UInt], Vec[UInt])] =
-    OptionWrapper(backendParams.basicDebugEn && param.isVecSchd, (Wire(Vec(1, UInt(log2Up(V0PhyRegs).W))), Wire(Vec(1, UInt(V0Data().dataWidth.W)))))
+  private val intDiffReadData: Option[Vec[UInt]] =
+    OptionWrapper(backendParams.basicDebugEn && param.isIntSchd, Wire(Vec(intSchdParams.numPregs, UInt(XLEN.W))))
+  private val fpDiffReadData: Option[Vec[UInt]] =
+    OptionWrapper(backendParams.basicDebugEn && param.isFpSchd, Wire(Vec(fpSchdParams.numPregs, UInt(XLEN.W))))
+  private val vfDiffReadData: Option[Vec[UInt]] =
+    OptionWrapper(backendParams.basicDebugEn && param.isVecSchd, Wire(Vec(vecSchdParams.numPregs, UInt(VLEN.W))))
+  private val v0DiffReadData: Option[Vec[UInt]] =
+    OptionWrapper(backendParams.basicDebugEn && param.isVecSchd, Wire(Vec(V0PhyRegs, UInt(V0Data().dataWidth.W))))
   private val vlDiffRead: Option[(Vec[UInt], Vec[UInt])] =
     OptionWrapper(backendParams.basicDebugEn && param.isVecSchd, (Wire(Vec(1, UInt(log2Up(VlPhyRegs).W))), Wire(Vec(1, UInt(VlData().dataWidth.W)))))
 
-  private val fpDiffReadData: Option[Vec[UInt]] =
-    OptionWrapper(backendParams.basicDebugEn && param.isFpSchd, Wire(Vec(32, UInt(XLEN.W))))
+  private val vecDiffNumPregs = 2 * (V0PhyRegs + vecSchdParams.numPregs)
   private val vecDiffReadData: Option[Vec[UInt]] =
-    OptionWrapper(backendParams.basicDebugEn && param.isVecSchd, Wire(Vec(64, UInt(64.W)))) // v0 = Cat(Vec(1), Vec(0))
+    OptionWrapper(backendParams.basicDebugEn && param.isVecSchd, Wire(Vec(vecDiffNumPregs, UInt(64.W)))) // v0 = Cat(Vec(1), Vec(0))
   private val vlDiffReadData: Option[UInt] =
     OptionWrapper(backendParams.basicDebugEn && param.isVecSchd, Wire(UInt(VlData().dataWidth.W)))
 
-
-  fpDiffReadData.foreach(_ := fpDiffRead
-    .get._2
-    .slice(0, 32)
-    .map(_(63, 0))
-  ) // fp only used [63, 0]
-  vecDiffReadData.foreach(_ := 
-    v0DiffRead
-    .get._2
-    .slice(0, 1)
-    .map(x => Seq(x(63, 0), x(127, 64))).flatten ++ 
-    vfDiffRead
-    .get._2
-    .slice(0, 31)
+  vecDiffReadData.foreach(_ :=
+    v0DiffReadData
+    .get
+    .map(x => Seq(x(63, 0), x(127, 64))).flatten ++
+    vfDiffReadData
+    .get
     .map(x => Seq(x(63, 0), x(127, 64))).flatten
   )
   vlDiffReadData.foreach(_ := vlDiffRead
@@ -307,32 +298,44 @@ class DataPath(implicit p: Parameters, params: BackendParams, param: SchdBlockPa
   if (param.isIntSchd) {
     IntRegFileSplit("IntRegFile", intSchdParams.numPregs, splitNum, intRfRaddr, intRfRdata.get, intRfWen, intRfWaddr, intRfWdata,
       bankNum = 1,
-      debugReadAddr = intDiffRead.map(_._1),
-      debugReadData = intDiffRead.map(_._2)
+      debugAllRData = intDiffReadData
     )
+    if (env.AlwaysBasicDiff || env.EnableDifftest) {
+      // Delay of PhyRegFile should be same as RenameTable
+      val difftest = DifftestModule(new DiffPhyIntRegState(intSchdParams.numPregs), delay = 2)
+      difftest.coreid := io.hartId
+      difftest.value := intDiffReadData.get
+    }
   }
   else if (param.isFpSchd) {
     FpRegFileSplit("FpRegFile", fpSchdParams.numPregs, splitNum, fpRfRaddr, fpRfRdata.get, fpRfWen, fpRfWaddr, fpRfWdata,
       bankNum = 1,
-      debugReadAddr = fpDiffRead.map(_._1),
-      debugReadData = fpDiffRead.map(_._2)
+      debugAllRData = fpDiffReadData
     )
+    if (env.AlwaysBasicDiff || env.EnableDifftest) {
+      val difftest = DifftestModule(new DiffPhyFpRegState(fpSchdParams.numPregs), delay = 2)
+      difftest.coreid := io.hartId
+      difftest.value := fpDiffReadData.get
+    }
   }
   else {
     VfRegFile("VfRegFile", vecSchdParams.numPregs, splitNum, vfRfRaddr, vfRfRdata.get, vfRfWen, vfRfWaddr, vfRfWdata,
-      debugReadAddr = vfDiffRead.map(_._1),
-      debugReadData = vfDiffRead.map(_._2)
+      debugAllRData = vfDiffReadData
     )
     VfRegFile("V0RegFile", V0PhyRegs, v0RfSplitNum, v0RfRaddr, v0RfRdata.get, v0RfWen, v0RfWaddr, v0RfWdata,
-      debugReadAddr = v0DiffRead.map(_._1),
-      debugReadData = v0DiffRead.map(_._2)
+      debugAllRData = v0DiffReadData
     )
     FpRegFile("VlRegFile", VlPhyRegs, vlRfRaddr, vlRfRdata.get, vlRfWen, vlRfWaddr, vlRfWdata,
       bankNum = 1,
       isVlRegfile = true,
       debugReadAddr = vlDiffRead.map(_._1),
       debugReadData = vlDiffRead.map(_._2)
     )
+    if (env.AlwaysBasicDiff || env.EnableDifftest) {
+      val difftest = DifftestModule(new DiffPhyVecRegState(vecDiffNumPregs), delay = 2)
+      difftest.coreid := io.hartId
+      difftest.value := vecDiffReadData.get
+    }
   }
 
   intRfWaddr := io.fromIntWb.map(x => RegEnable(x.addr, x.wen)).toSeq
@@ -398,30 +401,15 @@ class DataPath(implicit p: Parameters, params: BackendParams, param: SchdBlockPa
       vlRfRaddr(portIdx) := 0.U
   }
 
-
-  intDiffRead.foreach { case (addr, _) =>
-    addr := io.diffIntRat.get
-  }
-
-  fpDiffRead.foreach { case (addr, _) =>
-    addr := io.diffFpRat.get
-  }
-
-  vfDiffRead.foreach { case (addr, _) =>
-    addr := io.diffVecRat.get
-  }
-  v0DiffRead.foreach { case (addr, _) =>
-    addr := io.diffV0Rat.get
-  }
   vlDiffRead.foreach { case (addr, _) =>
     addr := io.diffVlRat.get
   }
 
   println(s"[DataPath] " +
-    s"has intDiffRead: ${intDiffRead.nonEmpty}, " +
-    s"has fpDiffRead: ${fpDiffRead.nonEmpty}, " +
-    s"has vecDiffRead: ${vfDiffRead.nonEmpty}, " +
-    s"has v0DiffRead: ${v0DiffRead.nonEmpty}, " +
+    s"has intDiffRead: ${intDiffReadData.nonEmpty}, " +
+    s"has fpDiffRead: ${fpDiffReadData.nonEmpty}, " +
+    s"has vecDiffRead: ${vfDiffReadData.nonEmpty}, " +
+    s"has v0DiffRead: ${v0DiffReadData.nonEmpty}, " +
     s"has vlDiffRead: ${vlDiffRead.nonEmpty}")
 
   // regcache
@@ -713,25 +701,6 @@ class DataPath(implicit p: Parameters, params: BackendParams, param: SchdBlockPa
     }
   }
 
-  if (env.AlwaysBasicDiff || env.EnableDifftest) {
-    val delayedCnt = 2
-    if (param.isIntSchd) {
-      val difftestArchIntRegState = DifftestModule(new DiffArchIntRegState, delay = delayedCnt)
-      difftestArchIntRegState.coreid := io.hartId
-      difftestArchIntRegState.value := intDiffRead.get._2
-    }
-    if (param.isFpSchd) {
-      val difftestArchFpRegState = DifftestModule(new DiffArchFpRegState, delay = delayedCnt)
-      difftestArchFpRegState.coreid := io.hartId
-      difftestArchFpRegState.value := fpDiffReadData.get
-    }
-    if (param.isVecSchd) {
-      val difftestArchVecRegState = DifftestModule(new DiffArchVecRegState, delay = delayedCnt)
-      difftestArchVecRegState.coreid := io.hartId
-      difftestArchVecRegState.value := vecDiffReadData.get
-    }
-  }
-
   val int_regcache_size = 48
   val int_regcache_tag = RegInit(VecInit(Seq.fill(int_regcache_size)(0.U(intSchdParams.pregIdxWidth.W))))
   val int_regcache_enqPtr = RegInit(0.U(log2Up(int_regcache_size).W))
@@ -980,10 +949,6 @@ class DataPathIO()(implicit p: Parameters, params: BackendParams, param: SchdBlo
     Output(UInt(RegCacheIdxWidth.W))
   )
 
-  val diffIntRat = if (params.basicDebugEn && param.isIntSchd) Some(Input(Vec(32, UInt(intSchdParams.pregIdxWidth.W)))) else None
-  val diffFpRat  = if (params.basicDebugEn && param.isFpSchd) Some(Input(Vec(32, UInt(fpSchdParams.pregIdxWidth.W)))) else None
-  val diffVecRat = if (params.basicDebugEn && param.isVecSchd) Some(Input(Vec(31, UInt(vecSchdParams.pregIdxWidth.W)))) else None
-  val diffV0Rat  = if (params.basicDebugEn && param.isVecSchd) Some(Input(Vec(1, UInt(log2Up(V0PhyRegs).W)))) else None
   val diffVlRat  = if (params.basicDebugEn && param.isVecSchd) Some(Input(Vec(1, UInt(log2Up(VlPhyRegs).W)))) else None
   val diffVl     = if (params.basicDebugEn && param.isVecSchd) Some(Output(UInt(VlData().dataWidth.W))) else None
 

src/main/scala/xiangshan/backend/datapath/WbArbiter.scala

@@ -3,7 +3,6 @@ package xiangshan.backend.datapath
 import org.chipsalliance.cde.config.Parameters
 import chisel3._
 import chisel3.util._
-import difftest.{DiffFpWriteback, DiffIntWriteback, DiffVecV0Writeback, DiffVecWriteback, DifftestModule}
 import utility.XSError
 import xiangshan.backend.BackendParams
 import xiangshan.backend.Bundles.{ExuOutput, WriteBackBundle}
@@ -396,49 +395,6 @@ class WbDataPath(params: BackendParams, schdParams: SchdBlockParams)(implicit p:
     sink.bits := source.bits
     source.ready := true.B
   }
-
-  // difftest
-  if (env.EnableDifftest || env.AlwaysBasicDiff) {
-    intWbArbiterOut.foreach(out => {
-      val difftest = DifftestModule(new DiffIntWriteback(IntPhyRegs))
-      difftest.coreid := io.fromTop.hartId
-      difftest.valid := out.fire && out.bits.rfWen
-      difftest.address := out.bits.pdest
-      difftest.data := out.bits.data
-    })
-  }
-
-  if (env.EnableDifftest || env.AlwaysBasicDiff) {
-    fpWbArbiterOut.foreach(out => {
-      val difftest = DifftestModule(new DiffFpWriteback(FpPhyRegs))
-      difftest.coreid := io.fromTop.hartId
-      difftest.valid := out.fire // all fp instr will write fp rf
-      difftest.address := out.bits.pdest
-      difftest.data := out.bits.data
-    })
-  }
-
-  if (env.EnableDifftest || env.AlwaysBasicDiff) {
-    vfWbArbiterOut.foreach(out => {
-      val difftest = DifftestModule(new DiffVecWriteback(VfPhyRegs))
-      difftest.coreid := io.fromTop.hartId
-      difftest.valid := out.fire
-      difftest.address := out.bits.pdest
-      difftest.data(0) := out.bits.data(63, 0)
-      difftest.data(1) := out.bits.data(127, 64)
-    })
-  }
-
-  if (env.EnableDifftest || env.AlwaysBasicDiff) {
-    v0WbArbiterOut.foreach(out => {
-      val difftest = DifftestModule(new DiffVecV0Writeback(V0PhyRegs))
-      difftest.coreid := io.fromTop.hartId
-      difftest.valid := out.fire
-      difftest.address := out.bits.pdest
-      difftest.data(0) := out.bits.data(63, 0)
-      difftest.data(1) := out.bits.data(127, 64)
-    })
-  }
 }