feat(top): adapt difftest interfaces for FPGA difftest

This change moves XSDiffTop instantiation into the Difftest for fpgaDiff.
DiffTop will generated with a SimTop wrapper, where DiffTest outputs,
together with XSTop's IO ports, AXI4 buses of memory/peripheral/DMA will
be exposed for external connection.

Temporarily, we still expose XSNoCDiffTop with appended Difftest IOs, and
generate XSTop and XSNoCTop with internal Difftest DPI-C, so as to avoid
extra TopIOs and mixed generated files. We will try to refactor them like
DiffTop later.(i.e. generate with a seperated Difftest)

Author: klin02

src/main/scala/top/Top.scala

@@ -20,7 +20,7 @@ package top
 import chisel3._
 import chisel3.util._
 import chisel3.experimental.dataview._
-import difftest.DifftestModule
+import difftest.{DifftestModule, DifftestTopIO, HasDiffTestInterfaces}
 import xiangshan._
 import utils._
 import utility._
@@ -43,10 +43,9 @@ import freechips.rocketchip.interrupts._
 import freechips.rocketchip.amba.axi4._
 import freechips.rocketchip.jtag.JTAGIO
 import chisel3.experimental.annotate
-import scala.collection.mutable.{Map}
 
-import difftest.common.DifftestWiring
-import difftest.util.Profile
+import scala.collection.mutable.Map
+import difftest.gateway.Gateway
 
 abstract class BaseXSSoc()(implicit p: Parameters) extends LazyModule
   with HasSoCParameter
@@ -460,11 +459,19 @@ class XSTop()(implicit p: Parameters) extends BaseXSSoc()
 class XSTileDiffTop(implicit p: Parameters) extends XSTop {
   //TODO: need to keep the same module name as XSNoCDiffTop
   override lazy val desiredName: String = "XSTop"
-  class XSTileDiffTopImp(wrapper: XSTop) extends XSTopImp(wrapper) {
-    DifftestWiring.createAndConnectExtraIOs()
-    Profile.generateJson("XiangShan")
-  }
 
+  class XSTileDiffTopImp(wrapper: XSTop) extends XSTopImp(wrapper) with HasDiffTestInterfaces {
+    override def cpuName: Option[String] = Some("XiangShan")
+    override def connectTopIOs(difftest: DifftestTopIO): Seq[Data] = {
+      Seq(wrapper.nmi.getWrappedValue) ++
+        dma.toSeq ++
+        Seq(
+          memory,
+          peripheral,
+          io
+        )
+    }
+  }
   override lazy val module = new XSTileDiffTopImp(this)
 }
 
@@ -484,7 +491,7 @@ object TopMain extends App {
     Generator.execute(firrtlOpts, soc.module, firtoolOpts)
   } else if (config(SoCParamsKey).UseXSTileDiffTop) {
     val soc = DisableMonitors(p => LazyModule(new XSTileDiffTop()(p)))(config)
-    Generator.execute(firrtlOpts, soc.module, firtoolOpts)
+    Generator.execute(firrtlOpts, DifftestModule.top(soc.module), firtoolOpts)
   } else {
     val soc = if (config(SoCParamsKey).UseXSNoCTop)
       DisableMonitors(p => LazyModule(new XSNoCTop()(p)))(config)
@@ -495,6 +502,8 @@ object TopMain extends App {
 
     // generate difftest bundles (w/o DifftestTopIO)
     if (enableDifftest) {
+      // TODO: Temporarily force XSTop to use internal DPI-C; will later split Top and Difftest like DiffTop
+      Gateway.setConfig("U")
       DifftestModule.collect("XiangShan")
     }
   }

src/test/scala/top/SimTop.scala

@@ -93,7 +93,7 @@ class XiangShanSim(implicit p: Parameters) extends Module with HasDiffTestInterf
   val uart = IO(new UARTIO)
   simMMIO.io.uart <> uart
 
-  override def connectTopIOs(difftest: DifftestTopIO): Unit = {
+  override def connectTopIOs(difftest: DifftestTopIO): Seq[Data] = {
     difftest.uart <> uart
 
     val hasPerf = !debugOpts.FPGAPlatform && debugOpts.EnablePerfDebug
@@ -105,6 +105,7 @@ class XiangShanSim(implicit p: Parameters) extends Module with HasDiffTestInterf
     val dump = if (hasPerf) WireDefault(difftest.perfCtrl.dump) else WireDefault(false.B)
 
     XSLog.collect(timer, logEnable, clean, dump)
+    Seq.empty
   }
 }