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submodule(difftest): refactor DiffTop, PhyReg and Refill #5221

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Merged
good-circle merged 14 commits into from
Dec 16, 2025
Merged

submodule(difftest): refactor DiffTop, PhyReg and Refill #5221

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e0a47c7
submodule(difftest): refactor DiffTop, PhyReg, Refill, PGO_BOLT
klin02 Nov 15, 2025
3567d5d
feat(top): adapt difftest interfaces for FPGA difftest
klin02 Nov 7, 2025
389d721
feat(difftest): replace ArchReg and Writeback with PhyRegState
klin02 Nov 15, 2025
afd2b3e
fix(difftest): add masked RefillEvent, disable for now
klin02 Nov 13, 2025
a01f518
fix(Makefile): unify PLDM and FPGA args under DEBUG_ARGS
klin02 Dec 1, 2025
5288496
feat(pdb): add difftest debugging commands for xspdb (#5175)
SFangYy Nov 26, 2025
a398897
feat(pdb): add files processing commands for xspdb (#5176)
SFangYy Nov 26, 2025
cb54b52
feat(pdb): Add memory read/write and backtrace commands (#5179)
SFangYy Nov 26, 2025
51caa6d
feat(pdb): add instruction and utility commands for xspdb (#5236)
SFangYy Nov 26, 2025
7e374f5
feat(pdb): add ELF symbol utilities, and trap controls for xspdb (#5239)
SFangYy Dec 2, 2025
8b252a0
feat(pdb): add register management commands and register-file load/parse
SFangYy Nov 27, 2025
22cf02f
feat(pdb): add asm and dasm command for xspdb
SFangYy Nov 27, 2025
988aff1
feat(pdb): add terminal ui for xspdb (#5299)
SFangYy Dec 3, 2025
bb37b9f
fix(pdb): resolve API incompatibility with difftest update
SFangYy Dec 2, 2025
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3 changes: 2 additions & 1 deletion .github/CODEOWNERS
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Original file line number Diff line number Diff line change
Expand Up @@ -44,5 +44,6 @@ huancun/ @linjuanZ

src/main/scala/top/ @Tang-Haojin

scripts/Makefile.pdb @yaozhicheng @forever043 @SFangYy @Tang-Haojin
scripts/pdb-run.py @yaozhicheng @forever043 @SFangYy @Tang-Haojin
scripts/xspdb/ @yaozhicheng @forever043 @SFangYy @Tang-Haojin
scripts/xspdb/ @yaozhicheng @SFangYy
17 changes: 9 additions & 8 deletions Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -148,8 +148,7 @@ endif

# public args sumup
RELEASE_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS)
DEBUG_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS)
override PLDM_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS)
override DEBUG_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS)

# co-simulation with DRAMsim3
ifeq ($(WITH_DRAMSIM3),1)
Expand Down Expand Up @@ -197,12 +196,14 @@ endif

# emu for the release version
RELEASE_ARGS += --fpga-platform --reset-gen --firtool-opt --ignore-read-enable-mem --firtool-opt "--default-layer-specialization=disable"
DEBUG_ARGS += --enable-difftest --firtool-opt "--default-layer-specialization=enable"
override PLDM_ARGS += --enable-difftest --firtool-opt "--default-layer-specialization=enable"
override DEBUG_ARGS += --firtool-opt "--default-layer-specialization=enable"
ifeq ($(FPGA), 1)
override DEBUG_ARGS += --fpga-platform --disable-all --remove-assert
else
override DEBUG_ARGS += --enable-difftest
endif
ifeq ($(RELEASE),1)
override SIM_ARGS += $(RELEASE_ARGS)
else ifeq ($(PLDM),1)
override SIM_ARGS += $(PLDM_ARGS)
else
override SIM_ARGS += $(DEBUG_ARGS)
endif
Expand All @@ -215,8 +216,8 @@ override SIM_ARGS += $(foreach c,$(call splitcomma,$(FIRRTL_COVER)),--extract-$(
endif

# use RELEASE_ARGS for TopMain by default
ifeq ($(PLDM), 1)
TOPMAIN_ARGS += $(PLDM_ARGS)
ifeq ($(or $(PLDM),$(FPGA)), 1)
TOPMAIN_ARGS += $(DEBUG_ARGS)
else
TOPMAIN_ARGS += $(RELEASE_ARGS)
endif
Expand Down
2 changes: 1 addition & 1 deletion difftest
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Submodule difftest updated 58 files
+1 −1 .github/workflows/format.yml
+46 −8 .github/workflows/main.yml
+8 −2 Makefile
+11 −6 README.md
+1 −5 config/config.h
+13 −1 emu.mk
+5 −1 fpga.mk
+1 −1 galaxsim.mk
+28 −3 gsim.mk
+1 −1 libso.mk
+1 −1 palladium.mk
+2 −2 pdb.mk
+136 −0 scripts/fpga/release.sh
+28 −25 src/main/scala/Bundles.scala
+72 −47 src/main/scala/DPIC.scala
+108 −18 src/main/scala/Delta.scala
+119 −85 src/main/scala/Difftest.scala
+26 −12 src/main/scala/Gateway.scala
+70 −122 src/main/scala/Preprocess.scala
+1 −1 src/main/scala/Replay.scala
+26 −7 src/main/scala/SimTop.scala
+1 −1 src/main/scala/Squash.scala
+26 −0 src/main/scala/fpga/AXI4.scala
+154 −0 src/main/scala/fpga/Host.scala
+14 −6 src/main/scala/util/Profile.scala
+5 −2 src/main/scala/util/Query.scala
+308 −0 src/test/csrc/common/args.cpp
+74 −0 src/test/csrc/common/args.h
+14 −3 src/test/csrc/common/compress.cpp
+0 −1 src/test/csrc/common/mpool.h
+1 −1 src/test/csrc/common/ram.cpp
+45 −0 src/test/csrc/difftest/diffstate.cpp
+162 −0 src/test/csrc/difftest/diffstate.h
+199 −281 src/test/csrc/difftest/difftest.cpp
+44 −194 src/test/csrc/difftest/difftest.h
+38 −37 src/test/csrc/difftest/refproxy.cpp
+32 −43 src/test/csrc/difftest/refproxy.h
+16 −318 src/test/csrc/emu/emu.cpp
+3 −52 src/test/csrc/emu/emu.h
+40 −62 src/test/csrc/fpga/fpga_main.cpp
+0 −1 src/test/csrc/fpga/xdma.h
+4 −4 src/test/csrc/plugin/runahead/runahead.cpp
+0 −4 src/test/csrc/plugin/xspdb/cpp/export.cpp
+0 −1 src/test/csrc/plugin/xspdb/cpp/export.h
+16 −3 src/test/csrc/plugin/xspdb/swig.i
+72 −52 src/test/csrc/vcs/vcs_main.cpp
+1 −0 src/test/scala/DifftestMain.scala
+37 −37 src/test/scala/DifftestTop.scala
+0 −211 src/test/vsrc/fpga/Difftest2AXI.v
+0 −52 src/test/vsrc/fpga/bram_port.v
+0 −56 src/test/vsrc/fpga/dual_buffer_bram.sv
+0 −1 src/test/vsrc/fpga_sim/xdma_axi.v
+0 −1 src/test/vsrc/fpga_sim/xdma_clock.v
+10 −24 src/test/vsrc/fpga_sim/xdma_wrapper.v
+12 −3 src/test/vsrc/vcs/DifftestEndpoint.sv
+17 −6 src/test/vsrc/vcs/top.v
+1 −1 vcs.mk
+29 −2 verilator.mk
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