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feat(top): allow extra CPU IO with connectTopIOs #713

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Merged
klin02 merged 1 commit into from
Nov 9, 2025
Merged

feat(top): allow extra CPU IO with connectTopIOs #713

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2 changes: 1 addition & 1 deletion src/main/scala/Difftest.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -572,7 +572,7 @@ object DifftestModule {
gateway
}

def top[T <: Module with HasDiffTestInterfaces](cpuGen: => T): SimTop[T] = new SimTop(cpuGen)
def top[T <: RawModule with HasDiffTestInterfaces](cpuGen: => T): SimTop[T] = new SimTop(cpuGen)

def generateSvhInterface(instances: Seq[DifftestBundle], numCores: Int): Unit = {
// generate interface by jsonProfile, single-core interface will be copied numCore times
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10 changes: 7 additions & 3 deletions src/main/scala/SimTop.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -61,11 +61,11 @@ class UARTIO extends Bundle {
trait HasDiffTestInterfaces {
def cpuName: Option[String] = None

def connectTopIOs(difftest: DifftestTopIO): Unit = {}
def connectTopIOs(difftest: DifftestTopIO): Seq[Data] = Seq.empty
}

// Top-level module for DiffTest simulation. Will be created by DifftestModule.top
class SimTop[T <: Module with HasDiffTestInterfaces](cpuGen: => T) extends Module {
class SimTop[T <: RawModule with HasDiffTestInterfaces](cpuGen: => T) extends Module {
val cpu = Module(cpuGen)

val cpuName = cpu.cpuName.getOrElse(cpu.getClass.getName.split("\\.").last)
Expand Down Expand Up @@ -102,7 +102,11 @@ class SimTop[T <: Module with HasDiffTestInterfaces](cpuGen: => T) extends Modul
}
}

cpu.connectTopIOs(difftest)
val cpuIO = cpu.connectTopIOs(difftest)
cpuIO.foreach { gen =>
val io = IO(chiselTypeOf(gen)).suggestName(gen.instanceName)
io <> gen
}

// There should not be anymore IOs
require(DifftestWiring.isEmpty, s"pending wires left: ${DifftestWiring.getPending}")
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