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Add class HdlDetect
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hdltools/hdl_detect.py

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#
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# Copyright (C) 2025 HDLtools Project
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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"""
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Module for detecting hardware description languages (HDL).
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This module provides the `HdlDetect` class, which can detect whether a given
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code is written in VHDL, Verilog, or SystemVerilog. It uses specific keywords
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and patterns to identify the language based on the code provided.
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"""
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import argparse
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import re
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class HdlDetect:
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"""
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Class to detect hardware description language (HDL) from a given code.
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"""
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def __init__(self, code=''):
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self.lang = None
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self.detect(code)
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def detect(self, code):
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"""Detect the HDL from the provided code."""
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self.code = code
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self.lang = None
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if 'entity' in self.code and 'module' not in self.code:
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self.lang = 'vhdl'
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elif 'entity' not in self.code and 'module' in self.code:
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self.lang = 'vlog'
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keywords = r'\blogic\b|\balways_ff\b|\balways_comb\b'
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if re.search(keywords, self.code):
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self.lang = 'slog'
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def is_vhdl(self):
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"""Returns True if the code is VHDL."""
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return self.lang == 'vhdl'
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def is_vlog(self):
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"""Returns True if the code is Verilog."""
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return self.lang == 'vlog'
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def is_slog(self):
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"""Returns True if the code is SystemVerilog."""
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return self.lang == 'slog'
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def is_xlog(self):
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"""Returns True if the code is Verilog or SystemVerilog."""
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return self.lang in ('vlog', 'slog')
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def get_lang(self):
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"""Returns the detected language."""
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return self.lang
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def __str__(self):
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return self.lang
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if __name__ == "__main__":
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parser = argparse.ArgumentParser()
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parser.add_argument('hdlfile')
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args = parser.parse_args()
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with open(args.hdlfile, 'r', encoding='utf-8') as fobj:
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text = fobj.read()
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obj = HdlDetect(text)
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print(obj.get_lang())

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