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pipeline.py: make_reset is updated
1 parent cdbd293 commit 06e20f2

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6 files changed

+20
-8
lines changed

6 files changed

+20
-8
lines changed

sample/tests/lib_pipeline/average/test_led.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -108,12 +108,12 @@
108108
109109
always @(posedge CLK) begin
110110
if(RST) begin
111-
y <= 0;
112111
_pipe_data_0 <= 0;
113112
_pipe_data_1 <= 0;
114113
_pipe_data_2 <= 0;
115114
_pipe_data_3 <= 0;
116115
_pipe_data_4 <= 0;
116+
y <= 0;
117117
end else begin
118118
_pipe_data_0 <= x;
119119
_pipe_data_1 <= _pipe_data_0;

sample/tests/lib_pipeline/average_valid/test_led.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -230,8 +230,6 @@
230230
231231
always @(posedge CLK) begin
232232
if(RST) begin
233-
y <= 0;
234-
vy <= 0;
235233
_pipe_data_0 <= 0;
236234
_pipe_valid_0 <= 0;
237235
_pipe_data_1 <= 0;
@@ -244,6 +242,8 @@
244242
_pipe_valid_4 <= 0;
245243
_pipe_data_5 <= 0;
246244
_pipe_valid_5 <= 0;
245+
y <= 0;
246+
vy <= 0;
247247
end else begin
248248
if(vx) begin
249249
_pipe_data_0 <= x;

sample/tests/lib_pipeline/average_validready/test_led.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -189,8 +189,6 @@
189189
190190
always @(posedge CLK) begin
191191
if(RST) begin
192-
y <= 0;
193-
vy <= 0;
194192
_pipe_data_0 <= 0;
195193
_pipe_valid_0 <= 0;
196194
_pipe_data_1 <= 0;
@@ -201,6 +199,8 @@
201199
_pipe_valid_3 <= 0;
202200
_pipe_data_4 <= 0;
203201
_pipe_valid_4 <= 0;
202+
y <= 0;
203+
vy <= 0;
204204
end else begin
205205
if((vx && _pipe_ready_0)) begin
206206
_pipe_data_0 <= x;

sample/tests/lib_pipeline/sum/led.py

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,8 @@ def mkLed():
1414
pipe = lib.Pipeline(m, 'pipe')
1515

1616
sum = m.Wire('sum', 32)
17+
18+
count = m.Reg('count', 32, initval=0)
1719

1820
px = pipe.input(x)
1921
psum = pipe.input(sum)
@@ -24,7 +26,7 @@ def mkLed():
2426

2527
m.Assign( y(sum) )
2628

27-
pipe.make_always(clk, rst)
29+
pipe.make_always(clk, rst, reset=[count.reset()], body=[count(count + 1)])
2830

2931
return m
3032

sample/tests/lib_pipeline/sum/test_led.py

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -105,14 +105,17 @@
105105
);
106106
107107
wire [32-1:0] sum;
108+
reg [32-1:0] count;
108109
reg [32-1:0] _pipe_data_0;
109110
assign sum = _pipe_data_0;
110111
assign y = sum;
111112
112113
always @(posedge CLK) begin
113114
if(RST) begin
115+
count <= 0;
114116
_pipe_data_0 <= 0;
115117
end else begin
118+
count <= count + 1;
116119
_pipe_data_0 <= x + sum;
117120
if(prst) begin
118121
_pipe_data_0 <= 0;

veriloggen/lib/pipeline.py

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -182,15 +182,22 @@ def make_prev(self, data, valid, ready, root_valid=None, width=None, initval=0):
182182

183183
return tmp_data, next_valid, tmp_ready
184184

185+
#---------------------------------------------------------------------------
186+
def make_reset(self):
187+
return self.par.make_reset()
188+
185189
#---------------------------------------------------------------------------
186190
def make_code(self):
187191
return self.par.make_code()
188192

189-
def make_always(self, clk, rst):
193+
#---------------------------------------------------------------------------
194+
def make_always(self, clk, rst, reset=(), body=()):
190195
self.m.Always(vtypes.Posedge(clk))(
191196
vtypes.If(rst)(
192-
self.m.make_reset()
197+
reset,
198+
self.make_reset()
193199
)(
200+
body,
194201
self.make_code()
195202
))
196203

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