pipeline.py: make_reset is updated

Author: shtaxxx

sample/tests/lib_pipeline/average/test_led.py

@@ -108,12 +108,12 @@
 
   always @(posedge CLK) begin
     if(RST) begin
-      y <= 0;
       _pipe_data_0 <= 0;
       _pipe_data_1 <= 0;
       _pipe_data_2 <= 0;
       _pipe_data_3 <= 0;
       _pipe_data_4 <= 0;
+      y <= 0;
     end else begin
       _pipe_data_0 <= x;
       _pipe_data_1 <= _pipe_data_0;

sample/tests/lib_pipeline/average_valid/test_led.py

@@ -230,8 +230,6 @@
 
   always @(posedge CLK) begin
     if(RST) begin
-      y <= 0;
-      vy <= 0;
       _pipe_data_0 <= 0;
       _pipe_valid_0 <= 0;
       _pipe_data_1 <= 0;
@@ -244,6 +242,8 @@
       _pipe_valid_4 <= 0;
       _pipe_data_5 <= 0;
       _pipe_valid_5 <= 0;
+      y <= 0;
+      vy <= 0;
     end else begin
       if(vx) begin
         _pipe_data_0 <= x;

sample/tests/lib_pipeline/average_validready/test_led.py

@@ -189,8 +189,6 @@
 
   always @(posedge CLK) begin
     if(RST) begin
-      y <= 0;
-      vy <= 0;
       _pipe_data_0 <= 0;
       _pipe_valid_0 <= 0;
       _pipe_data_1 <= 0;
@@ -201,6 +199,8 @@
       _pipe_valid_3 <= 0;
       _pipe_data_4 <= 0;
       _pipe_valid_4 <= 0;
+      y <= 0;
+      vy <= 0;
     end else begin
       if((vx && _pipe_ready_0)) begin
         _pipe_data_0 <= x;

sample/tests/lib_pipeline/sum/led.py

@@ -14,6 +14,8 @@ def mkLed():
     pipe = lib.Pipeline(m, 'pipe')
 
     sum = m.Wire('sum', 32)
+
+    count = m.Reg('count', 32, initval=0)
 
     px = pipe.input(x)
     psum = pipe.input(sum)
@@ -24,7 +26,7 @@ def mkLed():
 
     m.Assign( y(sum) )
 
-    pipe.make_always(clk, rst)
+    pipe.make_always(clk, rst, reset=[count.reset()], body=[count(count + 1)])
 
     return m
 

sample/tests/lib_pipeline/sum/test_led.py

@@ -105,14 +105,17 @@
 );
 
   wire [32-1:0] sum;
+  reg [32-1:0] count;
   reg [32-1:0] _pipe_data_0;
   assign sum = _pipe_data_0;
   assign y = sum;
 
   always @(posedge CLK) begin
     if(RST) begin
+      count <= 0;
       _pipe_data_0 <= 0;
     end else begin
+      count <= count + 1;
       _pipe_data_0 <= x + sum;
       if(prst) begin
         _pipe_data_0 <= 0;

veriloggen/lib/pipeline.py

@@ -182,15 +182,22 @@ def make_prev(self, data, valid, ready, root_valid=None, width=None, initval=0):
 
         return tmp_data, next_valid, tmp_ready
 
+    #---------------------------------------------------------------------------
+    def make_reset(self):
+        return self.par.make_reset()
+    
     #---------------------------------------------------------------------------
     def make_code(self):
         return self.par.make_code()
 
-    def make_always(self, clk, rst):
+    #---------------------------------------------------------------------------
+    def make_always(self, clk, rst, reset=(), body=()):
         self.m.Always(vtypes.Posedge(clk))(
             vtypes.If(rst)(
-                self.m.make_reset()
+                reset,
+                self.make_reset()
             )(
+                body,
                 self.make_code()
             ))