AxiMemoryModery supports a narrower bit-width than 8 in initial data configuration and set_memory method.

Author: shtaxxx

examples/thread_matmul/thread_matmul.py

@@ -12,8 +12,8 @@
 import veriloggen.thread as vthread
 import veriloggen.types.axi as axi
 
-axi_wordsize = 4
-data_wordsize = 4
+axi_datawidth = 32
+datawidth = 32
 
 a_offset = 0
 b_offset = 4096
@@ -31,7 +31,6 @@ def mkLed(matrix_size=16):
         timer.inc()
     )
 
-    datawidth = 32
     addrwidth = 10
     ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
     ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
@@ -106,11 +105,9 @@ def mkTest(memimg_name=None):
     n_raw_a = axi.shape_to_length(a_shape)
     n_raw_b = axi.shape_to_length(b_shape)
 
-    n_a = axi.memory_word_length(a_shape, data_wordsize)
-    n_b = axi.memory_word_length(b_shape, data_wordsize)
+    n_a = axi.shape_to_memory_size(a_shape, datawidth)
+    n_b = axi.shape_to_memory_size(b_shape, datawidth)
 
-    #a = np.arange(n_raw_a, dtype=np.int32).reshape(a_shape)
-    #b = np.arange(n_raw_b, dtype=np.int32).reshape(b_shape) + [n_a]
     a = np.zeros(a_shape, dtype=np.int64)
     b = np.zeros(b_shape, dtype=np.int64)
 
@@ -131,13 +128,13 @@ def mkTest(memimg_name=None):
                 b[y][x] = 0
 
     a_addr = a_offset
-    size_a = n_a * data_wordsize
+    size_a = n_a * datawidth // 8
     b_addr = b_offset
-    size_b = n_b * data_wordsize
+    size_b = n_b * datawidth // 8
 
-    mem = np.zeros([1024 * 1024 // axi_wordsize], dtype=np.int64)
-    axi.set_memory(mem, a, axi_wordsize, data_wordsize, a_addr)
-    axi.set_memory(mem, b, axi_wordsize, data_wordsize, b_addr)
+    mem = np.zeros([1024 * 1024 * 8 // axi_datawidth], dtype=np.int64)
+    axi.set_memory(mem, a, axi_datawidth, datawidth, a_addr)
+    axi.set_memory(mem, b, axi_datawidth, datawidth, b_addr)
 
     led = mkLed(matrix_size)
 
@@ -148,9 +145,9 @@ def mkTest(memimg_name=None):
     rst = ports['RST']
 
     memory = axi.AxiMemoryModel(m, 'memory', clk, rst,
-                                mem_datawidth=8 * axi_wordsize,
+                                mem_datawidth=axi_datawidth,
                                 memimg=mem, memimg_name=memimg_name)
-                                
+
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',

examples/thread_matmul_ipcore/thread_matmul_ipcore.py

@@ -13,8 +13,8 @@
 import veriloggen.types.axi as axi
 import veriloggen.types.ipcore as ipcore
 
-axi_wordsize = 4
-data_wordsize = 4
+axi_datawidth = 32
+datawidth = 32
 
 matrix_size = 16
 a_offset = 0
@@ -28,9 +28,7 @@ def mkLed():
     rst = m.Input('RST')
     led = m.OutputReg('led', 8, initval=0)
 
-    datawidth = 32
     addrwidth = 10
-
     ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
     ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
     ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth)
@@ -86,11 +84,9 @@ def mkTest(memimg_name=None):
     n_raw_a = axi.shape_to_length(a_shape)
     n_raw_b = axi.shape_to_length(b_shape)
 
-    n_a = axi.memory_word_length(a_shape, data_wordsize)
-    n_b = axi.memory_word_length(b_shape, data_wordsize)
+    n_a = axi.shape_to_memory_size(a_shape, datawidth)
+    n_b = axi.shape_to_memory_size(b_shape, datawidth)
 
-    #a = np.arange(n_raw_a, dtype=np.int32).reshape(a_shape)
-    #b = np.arange(n_raw_b, dtype=np.int32).reshape(b_shape) + [n_a]
     a = np.zeros(a_shape, dtype=np.int64)
     b = np.zeros(b_shape, dtype=np.int64)
 
@@ -111,13 +107,13 @@ def mkTest(memimg_name=None):
                 b[y][x] = 0
 
     a_addr = a_offset
-    size_a = n_a * data_wordsize
+    size_a = n_a * datawidth // 8
     b_addr = b_offset
-    size_b = n_b * data_wordsize
+    size_b = n_b * datawidth // 8
 
-    mem = np.zeros([1024 * 1024 // axi_wordsize], dtype=np.int64)
-    axi.set_memory(mem, a, axi_wordsize, data_wordsize, a_addr)
-    axi.set_memory(mem, b, axi_wordsize, data_wordsize, b_addr)
+    mem = np.zeros([1024 * 1024 * 8 // axi_datawidth], dtype=np.int64)
+    axi.set_memory(mem, a, axi_datawidth, datawidth, a_addr)
+    axi.set_memory(mem, b, axi_datawidth, datawidth, b_addr)
 
     led = mkLed()
 
@@ -128,7 +124,7 @@ def mkTest(memimg_name=None):
     rst = ports['RST']
 
     memory = axi.AxiMemoryModel(m, 'memory', clk, rst,
-                                mem_datawidth=8 * axi_wordsize,
+                                mem_datawidth=axi_datawidth,
                                 memimg=mem, memimg_name=memimg_name)
 
     memory.connect(ports, 'maxi')
@@ -183,7 +179,7 @@ def ctrl():
         for y in range(matrix_size):
             for x in range(matrix_size):
                 v = memory.read(
-                    c_offset + (y * matrix_size + x) * data_wordsize)
+                    c_offset + (y * matrix_size + x) * datawidth // 8)
                 if y == x and vthread.verilog.NotEql(v, (y + 1) * 2):
                     all_ok = False
                     print("NG [%d,%d] = %d" % (y, x, v))
@@ -241,7 +237,7 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None):
     rslt = run(filename='tmp.v')
     print(rslt)
 
-    memname = '_memory_memimg_.out'
+    memname = 'memimg_thread_matmul_ipcore.out'
     simcode = """
 reg [31:0] counter;
 always @(posedge sim_clk) begin

examples/thread_matmul_narrow/thread_matmul_narrow.py

@@ -12,8 +12,8 @@
 import veriloggen.thread as vthread
 import veriloggen.types.axi as axi
 
-axi_wordsize = 4
-data_wordsize = 8
+axi_datawidth = 32
+datawidth = 64
 
 a_offset = 0
 b_offset = 4096
@@ -31,13 +31,12 @@ def mkLed(matrix_size=16):
         timer.inc()
     )
 
-    datawidth = 64
     addrwidth = 10
     ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
     ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
     ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth)
     myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth //
-                         (data_wordsize // axi_wordsize))
+                         (datawidth // axi_datawidth))
 
     def matmul(matrix_size, a_offset, b_offset, c_offset):
         start_time = timer
@@ -107,11 +106,9 @@ def mkTest(memimg_name=None):
     n_raw_a = axi.shape_to_length(a_shape)
     n_raw_b = axi.shape_to_length(b_shape)
 
-    n_a = axi.memory_word_length(a_shape, data_wordsize)
-    n_b = axi.memory_word_length(b_shape, data_wordsize)
+    n_a = axi.shape_to_memory_size(a_shape, datawidth)
+    n_b = axi.shape_to_memory_size(b_shape, datawidth)
 
-    #a = np.arange(n_raw_a, dtype=np.int32).reshape(a_shape)
-    #b = np.arange(n_raw_b, dtype=np.int32).reshape(b_shape) + [n_a]
     a = np.zeros(a_shape, dtype=np.int64)
     b = np.zeros(b_shape, dtype=np.int64)
 
@@ -132,13 +129,13 @@ def mkTest(memimg_name=None):
                 b[y][x] = 0
 
     a_addr = a_offset
-    size_a = n_a * data_wordsize
+    size_a = n_a * datawidth // 8
     b_addr = b_offset
-    size_b = n_b * data_wordsize
+    size_b = n_b * datawidth // 8
 
-    mem = np.zeros([1024 * 1024 // axi_wordsize], dtype=np.int64)
-    axi.set_memory(mem, a, axi_wordsize, data_wordsize, a_addr)
-    axi.set_memory(mem, b, axi_wordsize, data_wordsize, b_addr)
+    mem = np.zeros([1024 * 1024 * 8 // axi_datawidth], dtype=np.int64)
+    axi.set_memory(mem, a, axi_datawidth, datawidth, a_addr)
+    axi.set_memory(mem, b, axi_datawidth, datawidth, b_addr)
 
     led = mkLed(matrix_size)
 
@@ -149,7 +146,7 @@ def mkTest(memimg_name=None):
     rst = ports['RST']
 
     memory = axi.AxiMemoryModel(m, 'memory', clk, rst,
-                                mem_datawidth=8 * axi_wordsize,
+                                mem_datawidth=axi_datawidth,
                                 memimg=mem, memimg_name=memimg_name)
 
     memory.connect(ports, 'myaxi')

examples/thread_matmul_wide/thread_matmul_wide.py

@@ -12,8 +12,8 @@
 import veriloggen.thread as vthread
 import veriloggen.types.axi as axi
 
-axi_wordsize = 8
-data_wordsize = 4
+axi_datawidth = 64
+datawidth = 32
 
 a_offset = 0
 b_offset = 4096
@@ -31,12 +31,12 @@ def mkLed(matrix_size=16):
         timer.inc()
     )
 
-    datawidth = 32
     addrwidth = 10
     ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
     ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
     ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth)
-    myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth * (axi_wordsize // data_wordsize))
+    myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth *
+                         (axi_datawidth // datawidth))
 
     def matmul(matrix_size, a_offset, b_offset, c_offset):
         start_time = timer
@@ -106,11 +106,9 @@ def mkTest(memimg_name=None):
     n_raw_a = axi.shape_to_length(a_shape)
     n_raw_b = axi.shape_to_length(b_shape)
 
-    n_a = axi.memory_word_length(a_shape, data_wordsize)
-    n_b = axi.memory_word_length(b_shape, data_wordsize)
+    n_a = axi.shape_to_memory_size(a_shape, datawidth)
+    n_b = axi.shape_to_memory_size(b_shape, datawidth)
 
-    #a = np.arange(n_raw_a, dtype=np.int32).reshape(a_shape)
-    #b = np.arange(n_raw_b, dtype=np.int32).reshape(b_shape) + [n_a]
     a = np.zeros(a_shape, dtype=np.int64)
     b = np.zeros(b_shape, dtype=np.int64)
 
@@ -131,13 +129,13 @@ def mkTest(memimg_name=None):
                 b[y][x] = 0
 
     a_addr = a_offset
-    size_a = n_a * data_wordsize
+    size_a = n_a * datawidth // 8
     b_addr = b_offset
-    size_b = n_b * data_wordsize
+    size_b = n_b * datawidth // 8
 
-    mem = np.zeros([1024 * 1024 // axi_wordsize], dtype=np.int64)
-    axi.set_memory(mem, a, axi_wordsize, data_wordsize, a_addr)
-    axi.set_memory(mem, b, axi_wordsize, data_wordsize, b_addr)
+    mem = np.zeros([1024 * 1024 * 8 // axi_datawidth], dtype=np.int64)
+    axi.set_memory(mem, a, axi_datawidth, datawidth, a_addr)
+    axi.set_memory(mem, b, axi_datawidth, datawidth, b_addr)
 
     led = mkLed(matrix_size)
 
@@ -148,8 +146,8 @@ def mkTest(memimg_name=None):
     rst = ports['RST']
 
     memory = axi.AxiMemoryModel(m, 'memory', clk, rst,
-                                datawidth=8 * axi_wordsize,
-                                mem_datawidth=8 * axi_wordsize,
+                                datawidth=axi_datawidth,
+                                mem_datawidth=axi_datawidth,
                                 memimg=mem, memimg_name=memimg_name)
 
     memory.connect(ports, 'myaxi')

examples/thread_stream_matmul/thread_stream_matmul.py

@@ -12,8 +12,8 @@
 import veriloggen.thread as vthread
 import veriloggen.types.axi as axi
 
-axi_wordsize = 4
-data_wordsize = 4
+axi_datawidth = 32
+datawidth = 32
 
 a_offset = 0
 b_offset = 4096
@@ -31,7 +31,6 @@ def mkLed(matrix_size=16):
         timer.inc()
     )
 
-    datawidth = 32
     addrwidth = 10
     ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
     ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
@@ -116,11 +115,9 @@ def mkTest(memimg_name=None):
     n_raw_a = axi.shape_to_length(a_shape)
     n_raw_b = axi.shape_to_length(b_shape)
 
-    n_a = axi.memory_word_length(a_shape, data_wordsize)
-    n_b = axi.memory_word_length(b_shape, data_wordsize)
+    n_a = axi.shape_to_memory_size(a_shape, datawidth)
+    n_b = axi.shape_to_memory_size(b_shape, datawidth)
 
-    #a = np.arange(n_raw_a, dtype=np.int32).reshape(a_shape)
-    #b = np.arange(n_raw_b, dtype=np.int32).reshape(b_shape) + [n_a]
     a = np.zeros(a_shape, dtype=np.int32)
     b = np.zeros(b_shape, dtype=np.int32)
 
@@ -141,13 +138,13 @@ def mkTest(memimg_name=None):
                 b[y][x] = 0
 
     a_addr = a_offset
-    size_a = n_a * data_wordsize
+    size_a = n_a * datawidth // 8
     b_addr = b_offset
-    size_b = n_b * data_wordsize
+    size_b = n_b * datawidth // 8
 
-    mem = np.zeros([1024 * 1024 // axi_wordsize], dtype=np.int64)
-    axi.set_memory(mem, a, axi_wordsize, data_wordsize, a_addr)
-    axi.set_memory(mem, b, axi_wordsize, data_wordsize, b_addr)
+    mem = np.zeros([1024 * 1024 * 8 // axi_datawidth], dtype=np.int64)
+    axi.set_memory(mem, a, axi_datawidth, datawidth, a_addr)
+    axi.set_memory(mem, b, axi_datawidth, datawidth, b_addr)
 
     led = mkLed(matrix_size)
 
@@ -158,7 +155,7 @@ def mkTest(memimg_name=None):
     rst = ports['RST']
 
     memory = axi.AxiMemoryModel(m, 'memory', clk, rst,
-                                mem_datawidth=8 * axi_wordsize,
+                                mem_datawidth=axi_datawidth,
                                 memimg=mem, memimg_name=memimg_name)
 
     memory.connect(ports, 'myaxi')

tests/extension/thread_/memorymodel_readwrite_narrow/thread_memorymodel_readwrite_narrow.py

@@ -106,13 +106,9 @@ def body(size, offset):
     return m
 
 
-def mkTest(memimg_name=None):
+def mkTest(memimg_name=None, axi_datawidth=32, datawidth=4, addrwidth=10):
     m = Module('test')
 
-    axi_datawidth = 32
-    datawidth = 4
-    addrwidth = 10
-
     # target instance
     led = mkLed(axi_datawidth, datawidth, addrwidth)
 

tests/extension/thread_/memorymodel_set_memory/Makefile

@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd