seq argument of seq can be skipped when it is not required.

Author: shtaxxx

tests/extension/dataflow_/graph_pass/test_dataflow_graph_pass.py

@@ -291,13 +291,6 @@
   assign zvalid = xvalid;
   assign xready = zready;
 
-  always @(posedge CLK) begin
-    if(RST) begin
-    end else begin
-    end
-  end
-
-
 endmodule
 """
 

tests/extension/dataflow_/pass/test_dataflow_pass.py

@@ -291,13 +291,6 @@
   assign zvalid = xvalid;
   assign xready = zready;
 
-  always @(posedge CLK) begin
-    if(RST) begin
-    end else begin
-    end
-  end
-
-
 endmodule
 """
 

tests/extension/dataflow_/pass_nocontrol/test_dataflow_pass_nocontrol.py

@@ -160,13 +160,6 @@
 
   assign zdata = xdata;
 
-  always @(posedge CLK) begin
-    if(RST) begin
-    end else begin
-    end
-  end
-
-
 endmodule
 """
 

tests/extension/seq_/countup_noreset/Makefile

@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

tests/extension/seq_/countup_noreset/seq_countup_noreset.py

@@ -0,0 +1,60 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    interval = m.Parameter('INTERVAL', 16)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led = m.OutputReg('LED', 8)
+    count = m.Reg('count', 32)
+    
+    seq = Seq(m, 'seq', clk)
+    seq.add( Systask('display', 'LED:%d count:%d', led, count) )
+    seq.add( count(count + 1), cond=count<interval-1 )
+    seq.add( count(0), cond=count==interval-1 )
+    seq.add( led(led + 1), cond=count==interval-1 )
+
+    seq.make_always()
+    
+    return m
+
+def mkTest():
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+    
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+    
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+    
+    #simulation.setup_waveform(m, uut)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+
+    init.add(
+        Delay(1000),
+        Systask('finish'),
+    )
+
+    return m
+    
+if __name__ == '__main__':
+    test = mkTest()
+    verilog = test.to_verilog()
+    print(verilog)

tests/extension/seq_/countup_noreset/test_seq_countup_noreset.py

@@ -0,0 +1,82 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import seq_countup_noreset
+
+expected_verilog = """
+module test #
+(
+  parameter INTERVAL = 16
+);
+
+  reg CLK;
+  reg RST;
+  wire [(8 - 1):0] LED;
+
+  blinkled
+  #(
+    .INTERVAL(INTERVAL)
+  )
+  uut
+  (
+    .CLK(CLK),
+    .RST(RST),
+    .LED(LED)
+  );
+
+
+  initial begin
+    CLK = 0;
+    forever begin
+      #5 CLK = (!CLK);
+    end
+  end
+
+  initial begin
+    RST = 0;
+    #100;
+    RST = 1;
+    #100;
+    RST = 0;
+    #1000;
+    $finish;
+  end
+endmodule
+
+module blinkled #
+(
+  parameter INTERVAL = 16
+)
+(
+  input CLK,
+  input RST,
+  output reg [(8 - 1):0] LED
+);
+
+  reg [(32 - 1):0] count;
+
+  always @(posedge CLK) begin
+    $display("LED:%d count:%d", LED, count);
+    if((count < (INTERVAL - 1))) begin
+      count <= (count + 1);
+    end 
+    if((count == (INTERVAL - 1))) begin
+      count <= 0;
+    end 
+    if((count == (INTERVAL - 1))) begin
+      LED <= (LED + 1);
+    end 
+  end
+endmodule
+"""
+def test():
+    test_module = seq_countup_noreset.mkTest()
+    code = test_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == code)

veriloggen/seq/seq.py

@@ -10,7 +10,7 @@
 
 class Seq(vtypes.VeriloggenNode):
     """ Sequential Logic Manager """
-    def __init__(self, m, name, clk, rst):
+    def __init__(self, m, name, clk, rst=None):
         self.m = m
         self.name = name
         self.clk = clk
@@ -104,12 +104,20 @@ def make_always(self, reset=(), body=()):
 
         part_reset = list(reset) + list(self.make_reset())
         part_body = list(body) + list(self.make_code())
-        self.m.Always(vtypes.Posedge(self.clk))(
-            vtypes.If(self.rst)(
-                part_reset,
-            )(
+
+        if not part_reset and not part_body:
+            pass
+        elif not part_reset or self.rst is None:
+            self.m.Always(vtypes.Posedge(self.clk))(
                 part_body,
-            ))
+            )
+        else:
+            self.m.Always(vtypes.Posedge(self.clk))(
+                vtypes.If(self.rst)(
+                    part_reset,
+                )(
+                    part_body,
+                ))
 
     #---------------------------------------------------------------------------
     def make_code(self):