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lib_pipeline is updated.
1 parent 06e20f2 commit 5f95748

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2 files changed

+19
-6
lines changed

2 files changed

+19
-6
lines changed

sample/tests/lib_pipeline/sum/led.py

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -11,11 +11,14 @@ def mkLed():
1111
y = m.Output('y', 32)
1212
prst = m.Input('prst')
1313

14-
pipe = lib.Pipeline(m, 'pipe')
15-
1614
sum = m.Wire('sum', 32)
17-
1815
count = m.Reg('count', 32, initval=0)
16+
17+
pipe = lib.Pipeline(m, 'pipe')
18+
par = lib.Parallel(m, 'par')
19+
20+
par.add( count(count+1) )
21+
par.add( count(0), cond=count==1023 )
1922

2023
px = pipe.input(x)
2124
psum = pipe.input(sum)
@@ -26,7 +29,8 @@ def mkLed():
2629

2730
m.Assign( y(sum) )
2831

29-
pipe.make_always(clk, rst, reset=[count.reset()], body=[count(count + 1)])
32+
pipe.make_always(clk, rst)
33+
par.make_always(clk, rst)
3034

3135
return m
3236

sample/tests/lib_pipeline/sum/test_led.py

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -112,17 +112,26 @@
112112
113113
always @(posedge CLK) begin
114114
if(RST) begin
115-
count <= 0;
116115
_pipe_data_0 <= 0;
117116
end else begin
118-
count <= count + 1;
119117
_pipe_data_0 <= x + sum;
120118
if(prst) begin
121119
_pipe_data_0 <= 0;
122120
end
123121
end
124122
end
125123
124+
always @(posedge CLK) begin
125+
if(RST) begin
126+
count <= 0;
127+
end else begin
128+
count <= count + 1;
129+
if(count == 1023) begin
130+
count <= 0;
131+
end
132+
end
133+
end
134+
126135
endmodule
127136
"""
128137

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