_list

Author: shtaxxx

tests/core/_list/Makefile

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+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

tests/core/_list/_list.py

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+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    width = m.Parameter('WIDTH', 8)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led = [ m.OutputReg('LED_%d' % i, width) for i in range(8) ]
+    count = m.Reg('count', 32)
+
+    m.Always(Posedge(clk))(
+        If(rst)(
+            count(0)
+        ).Else(
+            If(count == 1023)(
+                count(0)
+            ).Else(
+                count(count + 1)
+            )
+        ))
+
+    case_body = [ When(i)( led[i](count[width-1:0], blk=True) ) for i in range(8) ]
+    
+    m.Always()(
+        Case(count % 8)(
+            *case_body
+        )
+    )
+
+    return m
+
+if __name__ == '__main__':
+    led = mkLed()
+    verilog = led.to_verilog()
+    print(verilog)

tests/core/_list/test__list.py

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+from __future__ import absolute_import
+from __future__ import print_function
+import _list
+
+expected_verilog = """
+module blinkled #
+(
+  parameter WIDTH = 8
+)
+(
+  input CLK,
+  input RST,
+  output reg [WIDTH-1:0] LED_0,
+  output reg [WIDTH-1:0] LED_1,
+  output reg [WIDTH-1:0] LED_2,
+  output reg [WIDTH-1:0] LED_3,
+  output reg [WIDTH-1:0] LED_4,
+  output reg [WIDTH-1:0] LED_5,
+  output reg [WIDTH-1:0] LED_6,
+  output reg [WIDTH-1:0] LED_7
+);
+
+  reg [32-1:0] count;
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      count <= 0;
+    end else begin
+      if(count == 1023) begin
+        count <= 0;
+      end else begin
+        count <= count + 1;
+      end
+    end
+  end
+
+
+  always @(*) begin
+    case(count % 8)
+      0: begin
+        LED_0 = count[WIDTH-1:0];
+      end
+      1: begin
+        LED_1 = count[WIDTH-1:0];
+      end
+      2: begin
+        LED_2 = count[WIDTH-1:0];
+      end
+      3: begin
+        LED_3 = count[WIDTH-1:0];
+      end
+      4: begin
+        LED_4 = count[WIDTH-1:0];
+      end
+      5: begin
+        LED_5 = count[WIDTH-1:0];
+      end
+      6: begin
+        LED_6 = count[WIDTH-1:0];
+      end
+      7: begin
+        LED_7 = count[WIDTH-1:0];
+      end
+    endcase
+  end
+endmodule
+"""
+
+def test():
+    test_module = _list.mkLed()
+    code = test_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == code)