blocking substitution in always statements are fixed.

Author: shtaxxx

tests/core/blocking/Makefile

@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

tests/core/blocking/blocking.py

@@ -0,0 +1,39 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    width = m.Parameter('WIDTH', 8)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led = m.OutputReg('LED', width)
+    count = m.Reg('count', 32)
+
+    m.Always(Posedge(clk))(
+        If(rst)(
+            count(0)
+        ).Else(
+            If(count == 1023)(
+                count(0)
+            ).Else(
+                count(count + 1)
+            )
+        ))
+    
+    m.Always()(
+        led(count, blk=True)
+    )
+
+    return m
+
+if __name__ == '__main__':
+    led = mkLed()
+    verilog = led.to_verilog()
+    print(verilog)

tests/core/blocking/test_blocking.py

@@ -0,0 +1,44 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import blocking
+
+expected_verilog = """
+module blinkled #
+  (
+   parameter WIDTH = 8
+  )
+  (
+   input CLK, 
+   input RST, 
+   output reg [WIDTH-1:0] LED
+  );
+  reg [32-1:0] count;
+  always @(posedge CLK) begin
+    if(RST) begin        
+      count <= 0;
+    end else begin
+      if(count == 1023) begin
+        count <= 0;
+      end else begin
+        count <= count + 1;
+      end
+    end 
+  end 
+  always @(*) begin
+    LED = count;
+  end 
+endmodule
+"""
+
+def test():
+    test_module = blocking.mkLed()
+    code = test_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == code)

veriloggen/verilog/to_verilog.py

@@ -798,7 +798,8 @@ def visit_Subst(self, node):
         rdelay = self.visit(node.rdelay) if node.rdelay else None
         lvalue = vast.Lvalue(left)
         rvalue = vast.Rvalue(right)
-        if node.blk: vast.BlockingSubstitution(lvalue, rvalue, ldelay, rdelay)
+        if node.blk:
+            return vast.BlockingSubstitution(lvalue, rvalue, ldelay, rdelay)
         return vast.NonblockingSubstitution(lvalue, rvalue, ldelay, rdelay)
 
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