test/instance_ is updated for connect_same_name and connect_params/ports

Author: shtaxxx

tests/instance_/connect_ports/Makefile

@@ -0,0 +1,29 @@
+TARGET=*.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out tmp.v uut.vcd

tests/instance_/connect_ports/instance_connect_ports.py

@@ -0,0 +1,54 @@
+import sys
+import os
+import collections
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    width = m.Parameter('WIDTH', 8)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led = m.OutputReg('LED', width)
+    count = m.Reg('count', 32)
+
+    m.Always(Posedge(clk))(
+        If(rst)(
+            count(0)
+        ).Else(
+            If(count == 1023)(
+                count(0)
+            ).Else(
+                count(count + 1)
+            )
+        ))
+    
+    m.Always(Posedge(clk))(
+        If(rst)(
+            led( 0 )
+        ).Else(
+            If(count == 1023)(
+                led( led + 1 )
+            )
+        ))
+
+    return m
+
+def mkTop():
+    m = Module('top')
+    led = mkLed()
+    params= m.copy_params(led)
+    ports = m.copy_ports(led)
+    
+    m.Instance(led, 'inst_blinkled',
+               m.connect_params(led), m.connect_ports(led))
+    
+    return m
+
+if __name__ == '__main__':
+    top = mkTop()
+    verilog = top.to_verilog()
+    print(verilog)

tests/instance_/connect_ports/test_instance_connect_ports.py

@@ -0,0 +1,69 @@
+import instance_connect_ports
+
+expected_verilog = """
+module top #
+  (
+   parameter WIDTH = 8
+  )
+  (
+   input CLK, 
+   input RST, 
+   output [WIDTH-1:0] LED
+  );
+  blinkled #
+  (
+   .WIDTH(WIDTH)
+  )
+  inst_blinkled
+  (
+   .CLK(CLK),
+   .RST(RST),
+   .LED(LED)
+  );
+endmodule
+
+module blinkled #
+  (
+   parameter WIDTH = 8
+  )
+  (
+   input CLK, 
+   input RST, 
+   output reg [WIDTH-1:0] LED
+  );
+  reg [32-1:0] count;
+  always @(posedge CLK) begin
+    if(RST) begin        
+      count <= 0;
+    end else begin
+      if(count == 1023) begin
+        count <= 0;
+      end else begin
+        count <= count + 1;
+      end
+    end 
+  end 
+  always @(posedge CLK) begin
+    if(RST) begin        
+      LED <= 0;
+    end else begin
+      if(count == 1023) begin        
+        LED <= LED + 1;
+      end  
+    end 
+  end 
+endmodule
+"""
+
+def test_led():
+    test_module = instance_connect_ports.mkTop()
+    code = test_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == code)

tests/instance_/connect_same_name/Makefile

@@ -0,0 +1,29 @@
+TARGET=*.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out tmp.v uut.vcd

tests/instance_/connect_same_name/instance_connect_same_name.py

@@ -0,0 +1,54 @@
+import sys
+import os
+import collections
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    width = m.Parameter('WIDTH', 8)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led = m.OutputReg('LED', width)
+    count = m.Reg('count', 32)
+
+    m.Always(Posedge(clk))(
+        If(rst)(
+            count(0)
+        ).Else(
+            If(count == 1023)(
+                count(0)
+            ).Else(
+                count(count + 1)
+            )
+        ))
+    
+    m.Always(Posedge(clk))(
+        If(rst)(
+            led( 0 )
+        ).Else(
+            If(count == 1023)(
+                led( led + 1 )
+            )
+        ))
+
+    return m
+
+def mkTop():
+    m = Module('top')
+    led = mkLed()
+    params= m.copy_params(led)
+    ports = m.copy_ports(led)
+    
+    m.Instance(led, 'inst_blinkled',
+               connect_same_name(*params.values()), connect_same_name(*ports.values()))
+
+    return m
+
+if __name__ == '__main__':
+    top = mkTop()
+    verilog = top.to_verilog()
+    print(verilog)

tests/instance_/connect_same_name/test_instance_connect_same_name.py

@@ -0,0 +1,69 @@
+import instance_connect_same_name
+
+expected_verilog = """
+module top #
+  (
+   parameter WIDTH = 8
+  )
+  (
+   input CLK, 
+   input RST, 
+   output [WIDTH-1:0] LED
+  );
+  blinkled #
+  (
+   .WIDTH(WIDTH)
+  )
+  inst_blinkled
+  (
+   .CLK(CLK),
+   .RST(RST),
+   .LED(LED)
+  );
+endmodule
+
+module blinkled #
+  (
+   parameter WIDTH = 8
+  )
+  (
+   input CLK, 
+   input RST, 
+   output reg [WIDTH-1:0] LED
+  );
+  reg [32-1:0] count;
+  always @(posedge CLK) begin
+    if(RST) begin        
+      count <= 0;
+    end else begin
+      if(count == 1023) begin
+        count <= 0;
+      end else begin
+        count <= count + 1;
+      end
+    end 
+  end 
+  always @(posedge CLK) begin
+    if(RST) begin        
+      LED <= 0;
+    end else begin
+      if(count == 1023) begin        
+        LED <= LED + 1;
+      end  
+    end 
+  end 
+endmodule
+"""
+
+def test_led():
+    test_module = instance_connect_same_name.mkTop()
+    code = test_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == code)

tests/instance_/named_args/named_args.py renamed to tests/instance_/named_args/instance_named_args.py

@@ -1,4 +1,4 @@
-import named_args
+import instance_named_args
 
 expected_verilog = """
 module top #
@@ -56,7 +56,7 @@
 """
 
 def test_led():
-    test_module = named_args.mkTop()
+    test_module = instance_named_args.mkTop()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser

tests/instance_/named_args/test_named_args.py renamed to tests/instance_/named_args/test_instance_named_args.py

@@ -1,4 +1,4 @@
-import noname_args
+import instance_noname_args
 
 expected_verilog = """
 module top #
@@ -56,7 +56,7 @@
 """
 
 def test_led():
-    test_module = noname_args.mkTop()
+    test_module = instance_noname_args.mkTop()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser