associated clock

Author: shtaxxx

tests/extension/thread_/axi_dma_active_low_reset/thread_axi_dma_active_low_reset.py

@@ -15,7 +15,8 @@
 def mkLed():
     m = Module('blinkled')
     clk = m.Input('CLK')
-    # active low reset
+
+    # active low
     rst_x = m.Input('RST_X')
 
     # active low -> active high
@@ -111,7 +112,7 @@ def mkTest(memimg_name=None):
 
     clk = ports['CLK']
 
-    # active low reset
+    # active low
     rst_x = ports['RST_X']
 
     # active low -> active high

tests/extension/thread_/ipxact_axi_slave_lite/Makefile renamed to tests/extension/thread_/ipxact_axi/Makefile

@@ -3,16 +3,16 @@
 
 import os
 import veriloggen
-import thread_ipxact_axi_slave_lite
+import thread_ipxact_axi
 
 
 def test(request):
     veriloggen.reset()
 
     simtype = request.config.getoption('--sim')
 
-    rslt = thread_ipxact_axi_slave_lite.run(filename=None, simtype=simtype,
-                                            outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
+    rslt = thread_ipxact_axi.run(filename=None, simtype=simtype,
+                                 outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
 
     verify_rslt = rslt.splitlines()[-1]
     assert(verify_rslt == '# verify: PASSED')

tests/extension/thread_/ipxact_axi_slave_lite/test_thread_ipxact_axi_slave_lite.py renamed to tests/extension/thread_/ipxact_axi/test_thread_ipxact_axi.py

@@ -340,8 +340,9 @@ def mkBusParameterAssocBusIf(self, name):
 
         bus_name_list = []
         for bus_interface in self.bus_interfaces:
-            if (bus_interface.clk.module.is_input(bus_interface.clk)
-                    and bus_interface.clk.name == name):
+            if (isinstance(bus_interface.clk, vtypes._Variable) and
+                bus_interface.clk.module.is_input(bus_interface.clk.name) and
+                    bus_interface.clk.name == name):
                 bus_name_list.append(bus_interface.name)
 
         bus_names = ':'.join(bus_name_list)

tests/extension/thread_/ipxact_axi_slave_lite/thread_ipxact_axi_slave_lite.py renamed to tests/extension/thread_/ipxact_axi/thread_ipxact_axi.py

@@ -63,8 +63,17 @@ def to_ipxact(m, ip_name=None, ip_ver='1.0',
     bus_interfaces = masterbus + slavebus
 
     for bus_interface in bus_interfaces:
-        clk = bus_interface.clk.name if isinstance(bus_interface.clk, vtypes.Input) else None
-        rst = bus_interface.rst.name if isinstance(bus_interface.rst, vtypes.Input) else None
+        if (isinstance(bus_interface.clk, vtypes._Variable) and
+                bus_interface.clk.module.is_input(bus_interface.clk.name)):
+            clk = bus_interface.clk.name
+        else:
+            clk = None
+
+        if (isinstance(bus_interface.rst, vtypes._Variable) and
+                bus_interface.rst.module.is_input(bus_interface.rst.name)):
+            rst = bus_interface.rst.name
+        else:
+            rst = None
 
         if clk is not None and clk not in clk_ports:
             clk_ports[clk] = []