example of BRAM is added.

Author: shtaxxx

examples/bram/Makefile

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+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd 

examples/bram/bram.py

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+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+import math
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))
+
+from veriloggen import *
+import veriloggen.dataflow as dataflow
+
+def mkBram(datawidth=32, addrwidth=10, numports=2):
+    m = Module('BRAM%d' % numports)
+    
+    clk = m.Input('CLK')
+    ports = []
+    for i in range(numports):
+        addr = m.Input('ADDR%d' % i, addrwidth)
+        din = m.Input('DIN%d' % i, datawidth)
+        we = m.Input('WE%d' % i)
+        dout = m.Output('DOUT%d' % i, datawidth)
+        delay_addr = m.Reg('delay_ADDR%d' % i, addrwidth)
+        ports.append( (addr, din, we, dout, delay_addr) )
+
+    mem = m.Reg('mem', datawidth, length=2**addrwidth)
+
+    for i in range(numports):
+        addr, din ,we, dout, delay_addr = ports[i]
+        m.Always(Posedge(clk))(
+            If(we)(
+                mem[addr](din)
+            ),
+            delay_addr(addr)
+        )
+        m.Assign(dout(mem[delay_addr]))
+
+    return m
+
+def mkMain(n=128, datawidth=32, numports=2):
+    m = Module('main')
+
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+
+    addrwidth = int(math.log(n, 2)) * 2
+
+    bram = mkBram(datawidth, addrwidth, numports)
+
+    bram_ports = []
+    for i in range(numports):
+        addr = m.Reg('bram_addr%d' % i, addrwidth)
+        din = m.Reg('bram_din%d' % i, datawidth)
+        we = m.Reg('bram_we%d' % i)
+        dout = m.Wire('bram_dout%d' % i, datawidth)
+        bram_ports.append( [addr, din, we, dout] )
+
+    ports = [ clk ]
+    for bram_port in bram_ports:
+        ports.extend(bram_port)
+
+    # BRAM instance
+    m.Instance(bram, 'bram_inst', params=(), ports=ports)
+
+    # example how to access BRAM
+    fsm = FSM(m, 'fsm', clk, rst)
+    
+    for addr, din, we, dout in bram_ports:
+        fsm.add( addr(0), din(0), we(0) )
+
+    fsm.goto_next()
+
+    count = m.Reg('count', 32, initval=0)
+    for port, (addr, din, we, dout) in enumerate(bram_ports):
+        fsm.add( addr(count+port*n//numports), din(count), we(1), count.inc() )
+
+    fsm.goto_next(cond=count==n//numports-1)
+    
+    fsm.make_always()
+    
+    return m
+    
+def mkTest():
+    m = Module('test')
+    
+    # target instance
+    main = mkMain()
+    
+    # copy paras and ports
+    params = m.copy_params(main)
+    ports = m.copy_sim_ports(main)
+    
+    clk = ports['CLK']
+    rst = ports['RST']
+    
+    uut = m.Instance(main, 'uut',
+                     params=m.connect_params(main),
+                     ports=m.connect_ports(main))
+    
+    simulation.setup_waveform(m, uut, m.get_vars())
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+    
+    init.add(
+        Delay(1000 * 100),
+        Systask('finish'),
+    )
+
+    return m
+    
+if __name__ == '__main__':
+    test = mkTest()
+    verilog = test.to_verilog('tmp.v')
+    print(verilog)

examples/bram/test_bram.py

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+from __future__ import absolute_import
+from __future__ import print_function
+import bram
+
+expected_verilog = """
+module test
+(
+
+);
+
+  reg CLK;
+  reg RST;
+
+  main
+  uut
+  (
+    .CLK(CLK),
+    .RST(RST)
+  );
+
+
+  initial begin
+    $dumpfile("uut.vcd");
+    $dumpvars(0, uut, CLK, RST);
+  end
+
+
+  initial begin
+    CLK = 0;
+    forever begin
+      #5 CLK = !CLK;
+    end
+  end
+
+
+  initial begin
+    RST = 0;
+    #100;
+    RST = 1;
+    #100;
+    RST = 0;
+    #100000;
+    $finish;
+  end
+
+
+endmodule
+
+
+
+module main
+(
+  input CLK,
+  input RST
+);
+
+  reg [14-1:0] bram_addr0;
+  reg [32-1:0] bram_din0;
+  reg bram_we0;
+  wire [32-1:0] bram_dout0;
+  reg [14-1:0] bram_addr1;
+  reg [32-1:0] bram_din1;
+  reg bram_we1;
+  wire [32-1:0] bram_dout1;
+
+  BRAM2
+  bram_inst
+  (
+    .CLK(CLK),
+    .ADDR0(bram_addr0),
+    .DIN0(bram_din0),
+    .WE0(bram_we0),
+    .DOUT0(bram_dout0),
+    .ADDR1(bram_addr1),
+    .DIN1(bram_din1),
+    .WE1(bram_we1),
+    .DOUT1(bram_dout1)
+  );
+
+  reg [32-1:0] fsm;
+  localparam fsm_init = 0;
+  reg [32-1:0] count;
+  localparam fsm_1 = 1;
+  localparam fsm_2 = 2;
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      fsm <= fsm_init;
+      count <= 0;
+    end else begin
+      case(fsm)
+        fsm_init: begin
+          bram_addr0 <= 0;
+          bram_din0 <= 0;
+          bram_we0 <= 0;
+          bram_addr1 <= 0;
+          bram_din1 <= 0;
+          bram_we1 <= 0;
+          fsm <= fsm_1;
+        end
+        fsm_1: begin
+          bram_addr0 <= count + 0;
+          bram_din0 <= count;
+          bram_we0 <= 1;
+          count <= count + 1;
+          bram_addr1 <= count + 64;
+          bram_din1 <= count;
+          bram_we1 <= 1;
+          count <= count + 1;
+          if(count == 63) begin
+            fsm <= fsm_2;
+          end 
+        end
+      endcase
+    end
+  end
+
+
+endmodule
+
+
+
+module BRAM2
+(
+  input CLK,
+  input [14-1:0] ADDR0,
+  input [32-1:0] DIN0,
+  input WE0,
+  output [32-1:0] DOUT0,
+  input [14-1:0] ADDR1,
+  input [32-1:0] DIN1,
+  input WE1,
+  output [32-1:0] DOUT1
+);
+
+  reg [14-1:0] delay_ADDR0;
+  reg [14-1:0] delay_ADDR1;
+  reg [32-1:0] mem [0:16384-1];
+
+  always @(posedge CLK) begin
+    if(WE0) begin
+      mem[ADDR0] <= DIN0;
+    end 
+    delay_ADDR0 <= ADDR0;
+  end
+
+  assign DOUT0 = mem[delay_ADDR0];
+
+  always @(posedge CLK) begin
+    if(WE1) begin
+      mem[ADDR1] <= DIN1;
+    end 
+    delay_ADDR1 <= ADDR1;
+  end
+
+  assign DOUT1 = mem[delay_ADDR1];
+
+endmodule
+"""
+
+def test():
+    test_module = bram.mkTest()
+    code = test_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == code)