cpu/rp2350_common: create shared folder for RISCV & ARM

Author: AnnsAnns

cpu/riscv_common/Makefile

@@ -1,3 +1,3 @@
-DIRS = periph
+DIRS += periph
 
 include $(RIOTBASE)/Makefile.base

cpu/rp2350/doc.md

@@ -1,4 +1,4 @@
-@defgroup        cpu_rp2350 RP2350 MCUs
+@defgroup        cpu_rp2350_arm RP2350 MCUs
 @ingroup         cpu
 @brief           RP2350 MCU code and definitions
 

cpu/rp2350_arm/Makefile.include

@@ -0,0 +1,18 @@
+# CPU and architecture specific flags
+CFLAGS += -D$(CPU_MODEL)
+CFLAGS += -DROM_START_ADDR=$(ROM_START_ADDR)
+CFLAGS += -DRAM_START_ADDR=$(RAM_START_ADDR)
+
+# Linker flags
+LINKFLAGS += -mcpu=$(CPU_ARCH) -mthumb
+LINKFLAGS += -Wl,--gc-sections
+LINKFLAGS += -Wl,--start-group -lc -lm -Wl,--end-group
+
+# Vector table configuration
+VECTORS_O       ?= $(BINDIR)/cpu/vectors.o
+VECTORS_FILE    := $(RIOTCPU)/rp2350_common/vectors.c
+
+include $(RIOTCPU)/rp2350_common/Makefile.include
+
+# Include the base Cortex-M makefile
+include $(RIOTMAKE)/arch/cortexm.inc.mk

cpu/rp2350_common/Makefile

@@ -0,0 +1,3 @@
+DIRS += periph
+
+include $(RIOTBASE)/Makefile.base

cpu/rp2350_common/Makefile.dep

@@ -0,0 +1,4 @@
+USEMODULE += periph
+USEPKG += picosdk
+# We tell the build system that common needs to be built
+USEMODULE += rp2350_common

cpu/rp2350_common/Makefile.features

@@ -0,0 +1,2 @@
+FEATURES_PROVIDED += periph_gpio
+FEATURES_PROVIDED += periph_uart

cpu/rp2350_common/Makefile.include

@@ -0,0 +1,15 @@
+ROM_LEN         ?= 2097152    # = 2 MiB used in the RPi Pico
+ROM_OFFSET      := 0          # bootloader size
+RAM_LEN         := 0x82000    # 520kB = 532479 used in the RPi Pico 2350
+ROM_START_ADDR  := 0x10000000 # XIP Non-Secure address for rp2350
+RAM_START_ADDR  := 0x20000000 # Non-Secure RAM address for rp2350
+
+INCLUDES += -I$(RIOTCPU)/rp2350_common/include
+INCLUDES += -isystem$(RIOTBASE)/build/pkg/picosdk/src/rp2_common/cmsis/stub/CMSIS/Core/Include
+INCLUDES += -isystem$(RIOTBASE)/build/pkg/picosdk/src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include
+INCLUDES += -isystem$(RIOTBASE)/build/pkg/picosdk/src/rp2350/hardware_regs/include/hardware
+
+# Supported programmers and debuggers
+PROGRAMMERS_SUPPORTED := picotool openocd jlink
+PROGRAMMER ?= picotool
+OPENOCD_DEBUG_ADAPTER ?= dap

cpu/rp2350_common/clock.c

@@ -0,0 +1,71 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Tom Hert <[email protected]>
+ * SPDX-FileCopyrightText: 2025 HAW Hamburg
+ * SPDX-License-Identifier: LGPL-2.1-only
+ */
+
+/**
+ * @ingroup         cpu_rp2350
+ * @{
+ *
+ * @file
+ * @brief           Clock configuration implementation for the RP2350
+ *
+ * @author          Tom Hert <[email protected]>
+ */
+
+#include "periph_cpu.h"
+
+void clock_reset(void) {
+    /* Reset the clock system */
+    reset_component(RESET_PLL_SYS, RESET_PLL_SYS);
+}
+
+/**
+ * @brief Configures the XOSC and then sets CLK_SYS, PLL_SYS and CLK_PERI to it
+ * @warning Make sure to call clock_reset() before this function to reset the
+ * clock system
+ * @see RP2350 Docs Chapter 8, mostly 8.2 for more details
+ */
+void cpu_clock_init(void) {
+    /* Enable the XOSC */
+    xosc_start();
+
+    /* Setup the PLL using the XOSC as the reference clock. */
+    PLL_SYS->FBDIV_INT =
+    PLL_FEEDBACK_DIVIDER_VALUE; /* Set the feedback divider */
+
+    /* Set the post-dividers for the PLL output.*/
+    PLL_SYS->PRIM = PDIV;
+    /* Turn on PLL */
+    atomic_clear(&PLL_SYS->PWR,
+        PLL_PWR_PD_BITS | PLL_PWR_VCOPD_BITS | PLL_PWR_POSTDIVPD_BITS);
+
+    /* sleep 10ms to allow the PLL to stabilize */
+    xosc_sleep(10);
+
+    /* Based on the description in chapter 8 this is something that should be done
+     * However, it appears to cause issues and is not done by other examples on the
+     * internet. This needs to be investigated further. */
+
+    /* Wait for lock */
+    /* while (!(PLL_SYS->CS & PLL_CS_LOCK_BITS)) { */
+    /* Wait for the PLL to lock */
+    /* } */
+
+    /* AUXSRC = 0x0 7:5 && SRC == 0x0 0 */
+    CLOCKS->CLK_SYS_CTRL = CLK_SYS_PERI_CTRL_ENABLE_BIT;
+
+    /* This register contains one decoded bit for each of the clock sources
+     * enumerated in the CTRL SRC field. The bit does not directly correlate with
+     * the value of the SRC field For example 0x0 is the first bit while 0x1 is
+     * the second bit. In some way this makes sense, in some way I lost too much
+     * time on this. */
+    while (CLOCKS->CLK_SYS_SELECTED != CLK_SYS_SELECTED_PERI_FIELD_VALUE) {
+    }
+
+    /* AUXSRC = 0x0 -> CLK_SYS Indirectly through lower line */
+    CLOCKS->CLK_PERI_CTRL = CLK_PERI_CTRL_ENABLE_BIT;
+}
+
+/** @} */

cpu/rp2350_common/cpu.c

@@ -0,0 +1,56 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Tom Hert <[email protected]>
+ * SPDX-FileCopyrightText: 2025 HAW Hamburg
+ * SPDX-License-Identifier: LGPL-2.1-only
+ */
+
+/**
+ * @ingroup     cpu_rp2350
+ * @{
+ *
+ * @file
+ * @brief       Implementation of the CPU initialization for RP2350
+ *
+ * @author      Tom Hert <[email protected]>
+ * @}
+ */
+
+#include <sys/unistd.h>
+
+#include "board.h"
+#include "cpu.h"
+#include "clock_conf.h"
+#include "kernel_init.h"
+#include "periph/init.h"
+#include "periph/uart.h"
+#include "periph_conf.h"
+
+void gpio_reset(void)
+{
+    reset_component(RESET_PADS_BANK0, RESET_PADS_BANK0);
+    reset_component(RESET_IO_BANK0, RESET_IO_BANK0);
+}
+
+/**
+ * @brief Initialize the CPU, set IRQ priorities, clocks, peripheral
+ */
+void rp2350_init(void)
+{
+    /* Reset GPIO state */
+    gpio_reset();
+
+    /* Reset clock to default state */
+    clock_reset();
+
+    /* initialize the CPU clock */
+    cpu_clock_init();
+
+    /* initialize the early peripherals */
+    early_init();
+
+    /* trigger static peripheral initialization */
+    periph_init();
+
+    /* initialize the board */
+    board_init();
+}

cpu/rp2350_common/doc.md

@@ -0,0 +1,5 @@
+@defgroup        cpu_rp2350 RP2350 MCUs
+@ingroup         cpu
+@brief           RP2350 MCU code and definitions
+
+This module contains the code and definitions for MCUs of the RP2350 used by the Pi Pico 2.