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cpu/rp2350_common: create shared folder for RISCV & ARM

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# fixup! cpu/rp2350_common: create shared folder for RISCV & ARM

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Author: AnnsAnns

cpu/rp2350/doc.md

@@ -1,4 +1,4 @@
-@defgroup        cpu_rp2350 RP2350 MCUs
+@defgroup        cpu_rp2350_arm RP2350 MCUs
 @ingroup         cpu
 @brief           RP2350 MCU code and definitions
 

cpu/rp2350_common/include/compat_layer.h

@@ -1,11 +1,35 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Tom Hert <[email protected]>
+ * SPDX-FileCopyrightText: 2025 HAW Hamburg
+ * SPDX-License-Identifier: LGPL-2.1-only
+ */
+
 #pragma once
 
+/**
+ * @ingroup         cpu_rp2350
+ * @{
+ *
+ * @file
+ * @brief           Compatibility layer for different CPU architectures
+ *
+ * @author          Tom Hert <[email protected]>
+ */
+
 #include "periph_cpu.h"
 
 #ifdef RP2350_USE_RISCV
 #  include "xh3irq.h"
 #endif
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief     Enable the given IRQ
+ * @param[in] irq_no IRQ number to enable
+ */
 static inline void rp_irq_enable(uint32_t irq_no)
 {
 #ifdef RP2350_USE_RISCV
@@ -15,9 +39,18 @@ static inline void rp_irq_enable(uint32_t irq_no)
 #endif
 }
 
+/**
+ * @brief   Called upon the end of an ISR
+ */
 static inline void rp_end_isr(void)
 {
 #ifdef RP2350_USE_ARM
     cortexm_isr_end();
 #endif
 }
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */

cpu/rp2350_common/periph/uart.c

@@ -72,12 +72,13 @@ int uart_mode(uart_t uart, uart_data_bits_t data_bits, uart_parity_t parity,
     switch (parity) {
     case UART_PARITY_NONE:
         break;
-    // case UART_PARITY_EVEN:
-    //     io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_EPS_Msk | UART0_UARTLCR_H_PEN_Msk);
-    //     break;
-    // case UART_PARITY_ODD:
-    //     io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_PEN_Msk);
-    //     break;
+    /* Currently we don't support parity settings yet
+     * case UART_PARITY_EVEN:
+     *     io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_EPS_Msk | UART0_UARTLCR_H_PEN_Msk);
+     *     break;
+     * case UART_PARITY_ODD:
+     *     io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_PEN_Msk);
+     *     break; */
     default:
         return UART_NOMODE;
     }
@@ -110,11 +111,17 @@ void uart_init_pins(uart_t uart) {
     *(uint32_t *)calculate_gpio_io_ctrl_register_addr(uart_config[uart].tx_pin) = FUNCTION_SELECT_UART;
     *(uint32_t *)calculate_gpio_io_ctrl_register_addr(uart_config[uart].rx_pin) = FUNCTION_SELECT_UART;
     /* Clear the ISO bits */
-    atomic_clear((uint32_t *)calculate_gpio_pad_register_addr(uart_config[uart].tx_pin), PADS_BANK0_ISO_BITS);
-    atomic_clear((uint32_t *)calculate_gpio_pad_register_addr(uart_config[uart].rx_pin), PADS_BANK0_ISO_BITS);
+    atomic_clear(
+        calculate_gpio_pad_register_addr(uart_config[uart].tx_pin),
+        PADS_BANK0_ISO_BITS);
+    atomic_clear(
+        calculate_gpio_pad_register_addr(uart_config[uart].rx_pin),
+        PADS_BANK0_ISO_BITS);
 
     /* Set Input Enable Flag  */
-    atomic_set((uint32_t *)calculate_gpio_pad_register_addr(uart_config[uart].rx_pin), PADS_BANK0_GPIO0_IE_BITS);
+    atomic_set(
+        calculate_gpio_pad_register_addr(uart_config[uart].rx_pin),
+        PADS_BANK0_GPIO0_IE_BITS);
 
     /* We reset UART0 here, so we can be sure it is in a known state */
     _reset_uart(uart);
@@ -136,7 +143,11 @@ int uart_init(uart_t uart, uint32_t baud, uart_rx_cb_t rx_cb, void *arg) {
 
     uart_init_pins(uart);
 
-    if (uart_mode(uart, UART_DATA_BITS_8, UART_PARITY_NONE, UART_STOP_BITS_1) != UART_OK) {
+    if (uart_mode(
+            uart,
+            UART_DATA_BITS_8,
+            UART_PARITY_NONE,
+            UART_STOP_BITS_1) != UART_OK) {
         return UART_NOMODE;
     }