cpu/riscv_common: Add periph xh3irq support

Author: AnnsAnns

cpu/riscv_common/periph/xh3irq.c

@@ -1,17 +1,28 @@
-#include "xh3irq.h"
+/*
+ * SPDX-FileCopyrightText: 2025 Tom Hert <[email protected]>
+ * SPDX-FileCopyrightText: 2025 HAW Hamburg
+ * SPDX-License-Identifier: LGPL-2.1-only
+ */
+
 #include <stdio.h>
 
-uint32_t xh3irq_has_pending(void) {
+#include "bit.h"
+#include "xh3irq.h"
+
+uint32_t xh3irq_has_pending(void)
+{
     /*
      * Get MEIP which is the external interrupt pending bit
      * from the Machine Interrupt Pending Register address
      */
-    uint32_t meip = (read_csr(0x344) >> MEIP_OFFSET) & MEIP_MASK;
+     uint32_t mip_reg = read_csr(0x344);
+     uint32_t meip = bit_check32(&mip_reg, MEIP_OFFSET);
 
     return (meip != 0);
 }
 
-void xh3irq_handler(void) {
+void xh3irq_handler(void)
+{
     /*
      * Get MEINEXT at 0xbe4 which is the next highest interrupt to handle (Bit 2-10).
      * This will also automagically clear the interrupt (See 3.8.6.1.2.)
@@ -23,14 +34,15 @@ void xh3irq_handler(void) {
      */
     uint32_t meinext = (read_csr(0xBE4) >> MEINEXT_IRQ_OFFSET) & MEINEXT_MASK;
 
-    void (*isr)(void) = (void (*)(void))vector_cpu[meinext];
+    void (*isr)(void) = (void (*)(void)) vector_cpu[meinext];
 #ifdef DEVELHELP
     printf("Calling isr %p for irq %ld\n", isr, meinext);
 #endif
     isr();
 }
 
-void _meiea_set_req_bit(uint32_t irq_no, uint32_t bit_val) {
+void _meiea_set_req_bit(uint32_t irq_no, uint32_t bit_val)
+{
     uint32_t index = irq_no / INTERRUPT_ARRAY_MASK_OFFSET;
     uint32_t mask = bit_val << (irq_no % INTERRUPT_ARRAY_MASK_OFFSET);
 
@@ -45,7 +57,6 @@ void _meiea_set_req_bit(uint32_t irq_no, uint32_t bit_val) {
     __asm__ volatile(
         "csrs 0xbe0, %0\n"
         : : "r"(index | (mask << INTERRUPT_ARRAY_MASK_OFFSET))
-
     );
 }
 
@@ -70,6 +81,5 @@ void xh3irq_force_irq(uint32_t irq_no)
      */
     __asm__ volatile(
         "csrs 0xbe2, %0\n"
-        : : "r"(index | (mask << INTERRUPT_ARRAY_MASK_OFFSET))
-    );
+        : : "r"(index | (mask << INTERRUPT_ARRAY_MASK_OFFSET)));
 }