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cpu/rp2350_riscv: add xh3irq support
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20 files changed

+282
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‎boards/rpi-pico-2-riscv/board.c‎

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@@ -12,7 +12,4 @@ void board_init(void) {
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* This is needed, esp. when the LED is used via
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* the define macros */
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gpio_init(LED0_PIN_ID, GPIO_OUT);
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gpio_init(OSC_DEBUG_PIN_ID, GPIO_OUT);
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gpio_init(OSC_DEBUG_PIN_ID_2, GPIO_OUT);
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}

‎boards/rpi-pico-2-riscv/doc.md‎

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@defgroup boards_rpi_pico_2 Raspberry Pi Pico 2
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@defgroup boards_rpi_pico_2_riscv Raspberry Pi Pico 2
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@ingroup boards
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@brief Support for the RP2350 based Raspberry Pi Pico board
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@brief Support for the RP2350 RISCV based Raspberry Pi Pico board
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@warning The support for the Raspberry Pi Pico 2 is still in a very early stage!
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See [Known Issues](#rpi_pico_2_known_issues).
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See [Known Issues](#rpi_pico_2_riscv_known_issues).
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## Overview
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RIOT will download and install the Picotool locally in the RIOT folder.
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This process will take some minutes to complete.
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## Known Issues {#rpi_pico_2_known_issues}
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## Known Issues {#rpi_pico_2_riscv_known_issues}
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Currently RP2350 support is rather minimal,
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as such peripheral support is extremely limited.

‎boards/rpi-pico-2-riscv/include/board.h‎

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#pragma once
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/**
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* @ingroup boards_rpi_pico_2
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* @ingroup boards_rpi_pico_2_riscv
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* @{
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*
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* @file
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#define LED0_TOGGLE gpio_toggle(LED0_PIN_ID)
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#define LED0_NAME "LED(Green)"
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#define OSC_DEBUG_PIN_ID 15u
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#define OSC_DEBUG_PIN_ID_2 14u
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#ifdef __cplusplus
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extern "C" {
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#endif

‎boards/rpi-pico-2-riscv/include/periph_conf.h‎

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* @author Tom Hert <[email protected]>
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*/
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#include "kernel_defines.h"
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#include <stdint.h>
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#include "kernel_defines.h"
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#ifdef __cplusplus
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}
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#endif
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/** @} */

‎cpu/riscv_common/include/xh3irq.h‎

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@@ -57,12 +57,30 @@ extern const void *vector_cpu[CPU_IRQ_NUMOF];
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* @return 1 if there are pending interrupts, 0 otherwise
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*/
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uint32_t xh3irq_has_pending(void);
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/**
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* @brief The main IRQ handler, called from the assembly IRQ handler
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* @note This function must clear the pending interrupt in the interrupt controller
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*/
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void xh3irq_handler(void);
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/**
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* @brief Enable the given IRQ number
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* @param irq_no The IRQ number to enable
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*/
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void xh3irq_enable_irq(uint32_t irq_no);
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/**
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* @brief Disable the given IRQ number
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* @param irq_no The IRQ number to disable
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*/
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void xh3irq_disable_irq(uint32_t irq_no);
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/**
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* @brief Force the given IRQ number to be pending
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* @param irq_no The IRQ number to force
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* @note The IRQ still must be enabled to be handled
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*/
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void xh3irq_force_irq(uint32_t irq_no);
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#ifdef __cplusplus

‎cpu/rp2350_riscv/clock.c‎

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*/
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/**
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* @ingroup cpu_rp2350
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* @ingroup cpu_rp2350_riscv
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* @{
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*
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* @file

‎cpu/rp2350_riscv/cpu.c‎

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/*
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* Copyright (C) 2017, 2019 Ken Rabold, JP Bonn
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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* SPDX-FileCopyrightText: 2025 Tom Hert <[email protected]>
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* SPDX-FileCopyrightText: 2025 HAW Hamburg
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* SPDX-License-Identifier: LGPL-2.1-only
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*/
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/**
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* @ingroup cpu_fe310
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* @ingroup cpu_rp2350_riscv
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* @{
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*
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* @file cpu.c
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* @brief Implementation of the CPU initialization for SiFive FE310
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* @brief Implementation of the CPU initialization for RP2350
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*
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* @author Ken Rabold
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* @author Tom Hert <[email protected]>
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* @}
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*/
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‎cpu/rp2350_riscv/doc.md‎

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@defgroup cpu_fe310 SiFive fe310
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@ingroup cpu
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@brief SiFive fe310 RISC-V MCU specific implementation.
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@defgroup cpu_rp2350_riscv RP2350 RISCV MCUs
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@ingroup cpu
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@brief RP2350 RISCV MCU code and definitions
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This module contains SiFive fe310 specific code and definition.
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@see cpu_riscv_common
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This module contains the code and definitions for MCUs of the RP2350 RISCV family used by the Pi Pico 2.

‎cpu/rp2350_riscv/include/clock_conf.h‎

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#pragma once
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/**
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* @ingroup cpu_rp2350
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* @ingroup cpu_rp2350_riscv
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* @{
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*
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* @file
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* clock */
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#define CLK_SYS_PERI_CTRL_ENABLE_BIT (1u << 0u)
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/** Selected field value for the system clock control register
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* to select the peripheral clock */
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* to select the peripheral clock */
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#define CLK_SYS_SELECTED_PERI_FIELD_VALUE 2u
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/** RIOT core clock frequency defined as the CPU frequency */
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#define CLOCK_CORECLOCK MHZ(12u)

‎cpu/rp2350_riscv/include/core_cm33.h‎

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/*
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* SPDX-FileCopyrightText: 2025 Tom Hert <[email protected]>
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* SPDX-FileCopyrightText: 2025 HAW Hamburg
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* SPDX-License-Identifier: LGPL-2.1-only
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define __IM volatile const /*! Defines 'read only' structure member permissions */
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#define __OM volatile /*! Defines 'write only' structure member permissions */
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#define __IOM volatile /*! Defines 'read / write' structure member permissions */
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#ifdef __cplusplus
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}
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#endif

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