cpu/stm32: add initial STM32U3 and nucleo-u385rg-q support by itsadarshnair · Pull Request #22175 · RIOT-OS/RIOT

itsadarshnair · 2026-04-05T17:46:08Z

Contribution description

This PR adds initial support for the STM32U3 family and the NUCLEO-U385RG-Q board.

It includes:

initial STM32U3 CPU family support under cpu/stm32
board support for boards/nucleo-u385rg-q
basic clock and peripheral configuration required for bring-up

At the moment, this is an initial bring-up PR. The board boots and the LED blinking example was verified on hardware. Other peripherals and features may still be incomplete or untested.

At this stage, OpenOCD flashing support is not yet available. The board was programmed using STM32CubeProgrammer.

Testing procedure

The changes were tested with the examples/basic/blinky application on the nucleo-u385rg-q board.

Build:
bash
make -C examples/basic/blinky BOARD=nucleo-u385rg-q

Issues/PRs references

Progress for Tracking Issue #19264.

Declaration of AI-Tools / LLMs usage:

AI-Tools / LLMs that were used are:

ChatGPT for understanding the porting process, code generation/suggestions, with user review
Gemini for understanding the porting process and code suggestions, with user review

crasbe

Thank you for creating the Pull Request with the STM32U3 support.

This is the first review round that is has mostly style related comments. I will do a second round once everything style-wise is in order.

There are merge conflicts that have to be resolved before this can be merged.

crasbe · 2026-04-05T20:08:16Z

features.yaml

        - name: cpu_stm32u5
          help: The MCU has an STM32 U5 MCU
+        - name: cpu_stm32u3
+          help: The MCU has an STM32 U3 MCU


Suggested change

- name: cpu_stm32u5

help: The MCU has an STM32 U5 MCU

- name: cpu_stm32u3

help: The MCU has an STM32 U3 MCU

- name: cpu_stm32u3

help: The MCU has an STM32 U3 MCU

- name: cpu_stm32u5

help: The MCU has an STM32 U5 MCU

Keep the right order.

Fixed in the latest commit.

crasbe · 2026-04-05T20:08:45Z

cpu/stm32/stm32_mem_lengths.mk

    ifneq (, $(filter $(STM32_MODEL2), 7 8))
      RAM_LEN = 768K
      SRAM4_LEN = 16K
      BACKUP_RAM_ADDR = 0x40036400
      BACKUP_RAM_LEN = 0x2K
-    endif
+     endif


Suggested change

endif

endif

Whitespace error introduced.

Fixed in the latest commit.

crasbe · 2026-04-05T20:10:13Z

cpu/stm32/stm32_info.mk

 else ifeq (u5,$(CPU_FAM))
  CPU_CORE = cortex-m33
  SVD_MODEL := STM32U$(STM32_MODEL)
+else ifeq (u3,$(CPU_FAM))
+  CPU_CORE = cortex-m33
+  SVD_MODEL := STM32U$(STM32_MODEL)


Suggested change

else ifeq (u5,$(CPU_FAM))

CPU_CORE = cortex-m33

SVD_MODEL := STM32U$(STM32_MODEL)

else ifeq (u3,$(CPU_FAM))

CPU_CORE = cortex-m33

SVD_MODEL := STM32U$(STM32_MODEL)

else ifeq (u3,$(CPU_FAM))

CPU_CORE = cortex-m33

SVD_MODEL := STM32U$(STM32_MODEL)

else ifeq (u5,$(CPU_FAM))

CPU_CORE = cortex-m33

SVD_MODEL := STM32U$(STM32_MODEL)

Also here, keeping the order (although the others are not really ordered either...

Fixed in the latest commit.

crasbe · 2026-04-05T20:15:36Z

cpu/stm32/kconfigs/u3/Kconfig

+/*
+ * SPDX-FileCopyrightText: 2026 Adarsh Nair Mullachery
+ * SPDX-License-Identifier: LGPL-2.1-only
+ */


Suggested change

/*

* SPDX-FileCopyrightText: 2026 Adarsh Nair Mullachery

* SPDX-License-Identifier: LGPL-2.1-only

*/

# SPDX-FileCopyrightText: 2026 Technische Universität Hamburg

# SPDX-License-Identifier: LGPL-2.1-only

Kconfig uses hastags as comment indicators, not C++ style comments.

Also, as this is part of your Project Thesis, the copyright holder is the Technische Universität Hamburg. For files that have a Doxygen header, the Author is you but the Copyright header is TUHH.

Please adapt the other Kconfig files yourself.

Fixed in the latest commit.

crasbe · 2026-04-05T20:16:59Z

boards/nucleo-u385rg-q/include/periph_conf.h

Some files are missing Copyright headers. Please add the SPDX style Copyright header with TUHH copyright.
See #21515 (or as you did in the Kconfig files).

Fixed in the latest commit.

crasbe · 2026-04-05T20:23:12Z

cpu/stm32/include/periph/cpu_common.h

 /* if CPU has AHB/AHB1 bus */
 #if     defined(AHBPERIPH_BASE) || \
        defined(CPU_FAM_STM32F3)
            #define AHB_PERIPH_EN               RCC->AHBENR
+#elif   defined(CPU_FAM_STM32U3)
+            #define AHB1_PERIPH_EN              RCC->AHB1ENR1
+            #define AHB12_PERIPH_EN              RCC->AHB1ENR2


Suggested change

#define AHB12_PERIPH_EN RCC->AHB1ENR2

#define AHB12_PERIPH_EN RCC->AHB1ENR2

Whitespace error.

Fixed in the latest commit.

crasbe · 2026-04-05T20:24:14Z

cpu/stm32/include/periph/cpu_common.h

Please adapt the order of the #if defined() statements here that the U3 is before the U5.

Even though not everything is ordered, I'd like to maintain some level of order.

Please also adapt the other files accordingly.

Fixed in the latest commit.

crasbe · 2026-04-05T20:25:08Z

cpu/stm32/periph/pm.c

@@ -54,11 +54,10 @@
 #define PM_STOP_CONFIG  (PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS)
 #elif defined(CPU_FAM_STM32MP1)
 #define PM_STOP_CONFIG  (0)
-#elif defined(CPU_FAM_STM32U5)
+#elif defined(CPU_FAM_STM32U5) 


Suggested change

#elif defined(CPU_FAM_STM32U5)

#elif defined(CPU_FAM_STM32U5)

Whitespace error.

Fixed in the latest commit.

crasbe · 2026-04-05T20:26:19Z

cpu/stm32/Makefile.cmsis

@@ -31,6 +29,8 @@ PKG_VERSION_l1=dafdef897e29b4f5934f1e2b9de9957410435476
 PKG_VERSION_l4=013bf0e41256ffbc2b539676f2007d08b297a86a
 # v1.0.5
 PKG_VERSION_l5=a43f959bdb1e7449cbabe14356ca9309dbd48ad3
+# v1.2.0 (STM32U3 CMSIS)


Suggested change

# v1.2.0 (STM32U3 CMSIS)

# v1.2.0

Fixed in the latest commit.

crasbe · 2026-04-05T20:26:58Z

cpu/stm32/Makefile.features

@@ -64,6 +64,7 @@ STM32_WITH_VBAT = stm32f031% stm32f038% stm32f042% stm32f048% \
                  stm32l412% stm32l433% stm32l45% stm32l47% stm32l49% stm32l4r% \
                  stm32l5% \
                  stm32u5% \
+		              stm32u3% \


Suggested change

stm32u3% \

stm32u3% \

Wrong indentation.

Fixed in the latest commit.

crasbe · 2026-04-06T15:12:32Z

boards/nucleo-u385rg-q/include/periph_conf.h

+# SPDX-FileCopyrightText: 2026 Technische Universität Hamburg
+# SPDX-License-Identifier: LGPL-2.1-only


Suggested change

# SPDX-FileCopyrightText: 2026 Technische Universität Hamburg

# SPDX-License-Identifier: LGPL-2.1-only

/*

* SPDX-FileCopyrightText: 2026 Technische Universität Hamburg

* SPDX-License-Identifier: LGPL-2.1-only

*/

For C-files you have to use the C-style comments of course 😅

Please also adapt the other files.

Resolved it in latest commit

riot-ci · 2026-04-06T21:00:54Z

Murdock results

✔️ PASSED

f68d2cf fix remaining review issues

Success	Failures	Total	Runtime
11023	0	11025	11m:45s

Artifacts

Documentation preview

itsadarshnair requested review from MrKevinWeiss, aabadie, jia200x, kaspar030, leandrolanzieri and vincent-d as code owners April 5, 2026 17:46

github-actions bot added Platform: ARM Platform: This PR/issue effects ARM-based platforms Area: doc Area: Documentation Area: build system Area: Build system Area: boards Area: Board ports Area: cpu Area: CPU/MCU ports Area: Kconfig Area: Kconfig integration labels Apr 5, 2026

crasbe added Type: new feature The issue requests / The PR implemements a new feature for RIOT State: needs rebase State: The codebase was changed since the creation of the PR, making a rebase necessary labels Apr 5, 2026

crasbe reviewed Apr 5, 2026

View reviewed changes

crasbe reviewed Apr 6, 2026

View reviewed changes

Adarsh Nair Mullachery added 14 commits April 6, 2026 18:44

successfull make but not flashing

7c166e1

Fixed LED and Button

08ab81f

Makefile update nucleo64

f0a193c

Peripheral config no I2C, PWM

0c764a4

Update U3 BackupRAM support removed

7bcc597

Updated U3 flash page size and write block and alignment

1bf4666

reverting the changes made

9dd4397

Update clock config for stm32u3

3553408

AHB and APB mapping

6be1aa7

AHB and APB Updated

e4aa81d

U3 support updated

fbce260

Board name update

d500aee

Updated Doc for STM32U3RG-Q

e6ae97c

Add author and final updates

83e98e6

cpu/stm32: address review comments

ca4fb00

itsadarshnair force-pushed the stm32u385-port branch from 4072c14 to ca4fb00 Compare April 6, 2026 17:58

fix remaining review issues

f68d2cf

crasbe added CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR and removed State: needs rebase State: The codebase was changed since the creation of the PR, making a rebase necessary labels Apr 6, 2026

	#define AHB12_PERIPH_EN RCC->AHB1ENR2
	#define AHB12_PERIPH_EN RCC->AHB1ENR2

	#elif defined(CPU_FAM_STM32U5)
	#elif defined(CPU_FAM_STM32U5)

		# SPDX-FileCopyrightText: 2026 Technische Universität Hamburg
		# SPDX-License-Identifier: LGPL-2.1-only

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itsadarshnair commented Apr 5, 2026 • edited by crasbe Loading Uh oh! There was an error while loading. Please reload this page.

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Contribution description

Testing procedure

Issues/PRs references

Declaration of AI-Tools / LLMs usage:

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riot-ci commented Apr 6, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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itsadarshnair commented Apr 5, 2026 •

edited by crasbe

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riot-ci commented Apr 6, 2026 •

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