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@T410N T410N released this 13 Jul 02:33
· 249 commits to develop since this release
v1.0.0
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RV32I46F_5SP_SoC release v1.0.0

The very first release of basic_rv32s core design.

250711 RV32I46F_5SP_Final (1) RV32I46F_5SP core design's signal-level block diagram. 46F5SP_R2 drawio 46F5SP_SoC's signal-level block diagram.

What's included?

  • RV32I46F_5SP and its submodules' main core RTL code written in verilog.
  • Testbench source codes for each modules in core design.
  • Testbench results with vvp and vcd files.
    RV32I46F_5SP's top module testbench scenario is integrated in core memories.
  • 46F5SP_SoC top module which integrates RV32I46F_5SP core with GPIO and benchmark controllers.
  • Note that source code.zip provides the whole assets, attached RV32I46F_5SP_SoC.zip contains only RV32I46F_5SP and 46F5SP_SoC with testbenches.

What is this?

FPGA synthesizable RTL source codes of RV32I 5-Stage Pipelined processor RV32I46F_5SP and its SoC configuration modules.
You can simply run behavior simulation with iverilog and see waveforms via GTKwave or Sufer project.
In FPGA, you can debug the core module by interacting with buttons and watching the result by LEDs and UART TX communication. (115200baud)

  • Up button for continuous / sequential execution mode toggle.
  • Center button for next instruction (clk enable).
  • Down button for current pc value and instruction value.
  • Left button for register write address and register write value at WB stage.
  • Right button for ALU result in EX stage.

These GPIO settings can be modified at the Button Controller and DebugUARTController module.

For FPGA project in Vivado, get Package release for setup the environment with .xpr project file.

What's Changed

  • RV32I to PowerISA Implementation by @T410N in #1
  • Added explanations on how to use git commands by @ChoiCube84 in #2
  • ALU and its testbench for RV32I by @ChoiCube84 in #3
  • Delete goorm.manifest file and add .gitignore file by @ChoiCube84 in #4
  • Docs update by @T410N in #5
  • Add Program Counter module and Revise testbench for ALU by @ChoiCube84 in #6
  • Synchronizing develop branch with main branch by @ChoiCube84 in #7
  • Merge pull request #7 from RISC-KC/main by @ChoiCube84 in #8
  • Add Instruction Decoder module and its testbench by @ChoiCube84 in #9
  • Updating main branch by @ChoiCube84 in #10
  • Update Dev Log update, adding ISA and module explanation by @ChoiCube84 in #11
  • Implement basic structure of pc_controller module by @ChoiCube84 in #12
  • Implement basic structure of register file module by @ChoiCube84 in #13
  • ALU Control module complete by @ChoiCube84 in #14
  • Revise Instruction Decoder module and its testbench by @ChoiCube84 in #15
  • [Docs] Development Logs Update, Documents structure composition. by @T410N in #16
  • Revise ALU Control module and its testbench by @ChoiCube84 in #17
  • Add trap handling in PC Controller and testbench by @ChoiCube84 in #18
  • Implement testbenches for Program Counter and Register File by @ChoiCube84 in #19
  • Six modules implemented and tested by @ChoiCube84 in #20
  • Add chain of thought file (development log) by @ChoiCube84 in #21
  • Implement Immediate Generator module and its testbench by @ChoiCube84 in #22
  • Revise ALU Control module to also cover the store instructions by @ChoiCube84 in #23
  • Implement PCPlus4 module and its testbench by @ChoiCube84 in #24
  • Implement Instruction Memory module and its testbench by @ChoiCube84 in #25
  • 2025-01-30 devlog by @ChoiCube84 in #26
  • Implement Branch Logic module and its testbench by @ChoiCube84 in #27
  • Revise PC Controller to calculate target address for branch by itself by @ChoiCube84 in #28
  • 2025-01-31 devlog by @ChoiCube84 in #29
  • Add Datapath verification and revise RV32I47F.R1 to R7v2 by @T410N in #30
  • 2025-02-01 devlog by @ChoiCube84 in #31
  • 2025-02-04 devlog by @ChoiCube84 in #33
  • Implement Byte Enable Logic and its testbench by @ChoiCube84 in #32
  • Update devlog by @ChoiCube84 in #34
  • Implement Exception Detector module and its testbench by @ChoiCube84 in #35
  • Update devlog by @ChoiCube84 in #36
  • Update devlog by @ChoiCube84 in #37
  • Update RESEARCH and Development logs by @T410N in #38
  • Update devlog by @ChoiCube84 in #39
  • Update devlog by @ChoiCube84 in #40
  • Implement Control Unit module and its testbench by @ChoiCube84 in #41
  • Prepare core modules for simplified top module implementation by @ChoiCube84 in #42
  • Update devlog by @ChoiCube84 in #43
  • Revise PC Controller module to not change pc value when write_done signal is false by @ChoiCube84 in #44
  • Update devlog by @ChoiCube84 in #45
  • Update devlog by @ChoiCube84 in #46
  • Implement Data Memory module and its testbench by @ChoiCube84 in #47
  • Add Data Memory module to RV32I37F top module by @ChoiCube84 in #48
  • Update devlog by @ChoiCube84 in #49
  • [Docs] Update Devlog, CSR Listings by @T410N in #50
  • Update devlog by @ChoiCube84 in #51
  • [Docs] Update Devlog and Initialized Cache-memory Structure manual by @T410N in #52
  • [Docs]Update Devlog 250226 to 250302 by @T410N in #53
  • RV32I37F top module by @ChoiCube84 in #54
  • Implement CSR File and its testbench by @T410N in #55
  • Update devlog by @ChoiCube84 in #56
  • Implement RV32I37F top module and CSR File module by @ChoiCube84 in #57
  • Update devlog and RV32I37F verification log 250303 by @T410N in #58
  • [Feat] Implement RV32I43F top module and its testbench by @T410N in #62
  • Implement Instruction Cache and its testbench by @ChoiCube84 in #64
  • Revise Data Memory module by @ChoiCube84 in #65
  • Revise Data Memory to return data in 8 word chunk by @ChoiCube84 in #68
  • Implement Data Cache module by @ChoiCube84 in #70
  • [Feat] Implement Trap Controller and its testbench by @T410N in #73
  • [Feat] Correct rst signal to reset signal by @T410N in #74
  • Draft implementation of RV32I46F.v and its testbench by @T410N in #75
  • [Feat] Implement RV32I46F test scenario in Intruction Memory and its testbench by @T410N in #76
  • [Feat] Update TC about trap_done signal by @T410N in #77
  • [Feat] Debugging RV32I46F 01 by @T410N in #78
  • [Feat] Debug Trap Controller PTH 1CLK delay by @T410N in #79
  • [Feat] modify wrong data value in instruction memory data 1024 by @T410N in #83
  • [Feat] implement pcc micro opcode for next_pc race issue by @T410N in #84
  • [Feat] implement PCC micro opcode for next_pc race issue by @T410N in #80
  • [Feat] Modified logic to detect source value of next_pc signal in advance by @T410N in #81
  • [Feat] implement branch target address calculation in branch_logic by @T410N in #82
  • [Feat] Modified signal name by revising instr signal to instruction signal by @T410N in #85
  • [Feat] Modify MRET trap address alignment and refactor existing trap controller FSM design by @T410N in #87
  • [Feat] Modify Trap Controller FSM combinational logic by @T410N in #88
  • [Feat] Modify wrong encoding of mret instruction and add instruction for EBREAK by @T410N in #89
  • [Feat] Implement RV32I46F top module and its testbench by @T410N in #90
  • [Feat] modify branch target calculation logic position in branch logic module and its testbench by @T410N in #91
  • [Feat] Modify abbreviated variable names in Exception Detector to their full descriptive forms. by @T410N in #92
  • [Feat] Separate non cache based data memory and cache based data memory for RV32I46F by @T410N in #93
  • [Feat] Modified Exception Detector signal name and its testbench for revised standalone Data Memory module by @T410N in #94
  • [Feat] Implement 5 Stage Pipeline registers by @T410N in #95
  • [Feat] Add rd signal from to each pipeline registers by @T410N in #96
  • [Feat] Revise PC Controller to non PCC micro opcode structure by @T410N in #97
  • [Feat] Revise PC Controller by adding branch target signal and its testbench by @T410N in #98
  • [Feat] Implement Hazard_Unit and its testbench by @T410N in #99
  • [Feat] Implement Forward Unit and its testbench by @T410N in #100
  • [Feat] Implement 2-bit FSM Branch Predictor and its testbench by @T410N in #101
  • [Feat] Revise Control Unit to non PCC micro opcode structure by @T410N in #102
  • [Feat] Revise MEM_WB_Register read_data signal name to BERF_WD and its testbench by @T410N in #103
  • [Feat] Revise Forward_Unit read_data signal name to BERF_WD and its testbench by @T410N in #104
  • [Feat] Debug 03 Revise unmatched signals to match in RV32I46F_5SP top-module design by @T410N in #105
  • [Feat] Debug 04 : Remove all waveform-identifiable x and z values by correcting signal declarations in the RV32I46F_5SP top module by @T410N in #106
  • [Feat] Add branch_prediction_miss logic and remove branch_target signal and logic and its testbench by @T410N in #107
  • [Feat] Revise PC Controller next_pc signal source priority by @T410N in #108
  • [Feat] Add pc and instruction signals to debug each phase of pipeline registers by @T410N in #110
  • [Feat] Instanciate debug signals and remove unused signal instance by @T410N in #109
  • [Feat] Add ID_EX_flush signal for proper PTH operation and implement its testbench by @T410N in #112
  • [Feat] Add ID_EX_flush signal for proper PTH operation when misaligned by @T410N in #111
  • [Feat] Revise Trap Controller ECALL instruction mepc CSR write logic by @T410N in #125
  • [Feat] Revise RV32I46F_5SP's top-module logic and apply changes from debugging by @T410N in #113
  • [Feat] Revise Branch Logic by adding actual branch target address calculation logic by @T410N in #115
  • [Feat] Revise Branch Predictor by removing EX branch target calculation logic and its testbench by @T410N in #116
  • [Feat] Revise CSR File mtvec csr to read-only and add bypass logic by @T410N in #117
  • [Feat] Revise Exception Detector by adding EX phase opcode and branch estimation signal for proper trap handling by @T410N in #118
  • [Feat] Revise Forward Unit by additionally implementing WB phase and CSR value forwarding by @T410N in #119
  • [Feat] Revise Hazard Unit by implementing data hazard detection logic on MEM WB phase and CSR by @T410N in #120
  • [Feat] Revise Instruction Memory testbench scenario for RV32I46F_5SP by @T410N in #121
  • [Feat] Revise PC Controller by dualizing the branch_target signal and priortizing conditions for the next_pc decision by @T410N in #122
  • [Feat] Revise Pipeline Registers by adding control signals and pipeline required value signals by @T410N in #123
  • [Feat] Revise Register File by adding bypassing logic when read_register is same with write_register by @T410N in #124
  • [Feat] Added missing mtvec default value reset logic by @T410N in #126
  • [Feat] Revise Branch Predictor by removing unnecessary register variable and its testbench by @T410N in #128
  • [Feat] Revise Pipeline Register raw_imm value width by @T410N in #127
  • [Feat] Implement and RV32I46F_5SP top module and its testbench waveform verification by @T410N in #129
  • [Feat] Revise RV32I46F_5SP top-module RTL code by removing non-used signals and instances and its testbench by @T410N in #131
  • [Feat] Revise Hazard Unit by removing unused clock and reset signal by @T410N in #130
  • [Feat] Revise Hazard Unit by removing unused signal EX_register_write_enable by @T410N in #133
  • [Feat] Revise Trap Controller latch infer issue and multi-driven issue by @T410N in #132
  • [Feat] Revise Branch Predictor by solving branch_target signal multi-driven issue by @T410N in #134
  • [Feat] Revise Byte Enable Logic by properly allocating bit width for misalignment detection address signal by @T410N in #135
  • [Feat] Implement Misaligned Memory Address Access Exception detector and revise trap header by @T410N in #136
  • [Feat] Implement Misaligned Memory Address Access Exception in RV32I46F_5SP and its testbench by @T410N in #140
  • [Feat] Revise Instruction Memory by adding Misaligned Memory Address Access exception scenario by @T410N in #137
  • [Feat] Revise MEM_WB_Register by adding pipeline_stall signal and its logic by @T410N in #138
  • [Feat] Revise Trap Controller to support Misaligned Memory Address Exception by @T410N in #139
  • [Feat] Restore Trap Controller latch infer issue and multi-driven issue revision by @T410N in #141
  • [Feat] Revise Control Unit latch infer issue in FPGA implementation. by @T410N in #142
  • [Feat] Revise Instruction Decoder latch infer issue in FPGA implementation by @T410N in #143
  • [Feat] Revise Trap Controller and trap header file by adding standby mode and PTH done flush by @T410N in #144
  • [Feat] Revise CSR File implementation from Asynchronous to Synchronous by @T410N in #145
  • [Feat] Revise Control Unit by adding csr_ready signal for Synchronous CSR File by @T410N in #146
  • [Feat] Revise Byte Enable Logic by removing address misalignment detection logic by @T410N in #147
  • [Feat] Revise Exception Detector to separately handle MISALIGNED STORE and LOAD exceptions by @T410N in #148
  • [Feat] Revise ALU Controller latch infer issue in FPGA implementation and its testbench by @T410N in #149
  • [Feat] Revise Hazard Unit by supporting csr_ready pipeline stall and PTH precisely by @T410N in #150
  • [Feat] Revise Pipeline Registers by refactoring stall logic and reintroducing flush logic by @T410N in #151
  • [Feat] Revise Instruction Memory by adding Misaligned store load trap handler and test expectation values by @T410N in #152
  • [Feat] Revise Register File by adding logic for default zero value initializing by @T410N in #153
  • [Feat] Revise RV32I46F_5SP by implementing Synchronous CSR File in top module design and its testebench by @T410N in #154
  • [Feat] Revise Trap Controller PTH for Synchronous Exception Detector by @T410N in #155
  • [Feat] Revise Exception Detector output to Synchronous for FPGA Implementation by @T410N in #156
  • [Feat] Revise Hazard Unit for Synchronous Exception Detector by @T410N in #157
  • [Feat] Revise RV32I46F_5SP Synchronous Exception Detector for FPGA implementation and its testbench by @T410N in #158
  • [Feat] Implement Register File Debug module for 46F5SP_SoC_TOP FPGA verification and debugging by @T410N in #159
  • [Feat] Revise Program Counter by adding clock enable signal for 46F5SP_SoC_TOP FPGA verification and debugging by @T410N in #160
  • [Feat] Revise Hazard Unit by adding clock enable signal for 46F5SP_SoC_TOP FPGA verification and debugging by @T410N in #161
  • [Feat] Revise Exception Detector by adding clock enable signal for 46F5SP_SoC_TOP FPGA verification and debugging by @T410N in #162
  • [Feat] Revise Pipeline Registers separating reset flush logic and adding clock enable signal by @T410N in #163
  • [Feat] Revise Data Memory adding clock enable signal for 46F5SP_SoC_TOP FPGA verification and debugging by @T410N in #164
  • [Feat] Revise CSR File adding clock enable signal for 46F5SP_SoC_TOP FPGA verification and debugging by @T410N in #165
  • [Feat] Revise Branch Predictor by adding clock enable signal for FPGA verification and debugging by @T410N in #166
  • [Feat] Implement RV32I46F_5SP_Debug core design by adding output signals for debugging by @T410N in #167
  • [Feat] Implement Button Controller for 46F5SP_SoC_TOP FPGA verification and debugging by @T410N in #168
  • [Feat] Implement UART TX for 46F5SP_SoC_TOP FPGA verification and debugging by @T410N in #170
  • [Feat] Implement Debug UART Controller for 46F5SP SoC TOP FPGA verification and debugging by @T410N in #171
  • [Feat] Implement RV32I46F_5SP FPGA debug SoC Top module for FPGA verification by @T410N in #172
  • [Feat] Revise RV32I46F 5SP Debug ID EX Register instance misconnected signal csr_read_data to csr_read_out by @T410N in #174
  • [Feat] Revise Trap Controller by adding clock enable signal for 46F5SP_SoC_TOP FPGA verification and debugging by @T410N in #173
  • [Feat] Revise PC Controller next pc logic source priorities by @T410N in #176
  • [Feat] Revise Instruction Memory by bringing back old testbenches by @T410N in #177

Full Changelog: https://github.com/RISC-KC/basic_rv32s/commits/v1.0.0

Contributors

T410N and ChoiCube84
Assets 3
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