@@ -304,11 +304,7 @@ DxlError Dynamixel::SetDxlReadItems(
304304
305305DxlError Dynamixel::SetMultiDxlRead ()
306306{
307- if (read_data_list_.size () < 2 ) {
308- read_type_ = SYNC;
309- } else {
310- read_type_ = checkReadType ();
311- }
307+ read_type_ = checkReadType ();
312308
313309 fprintf (stderr, " Dynamixel Read Type : %s\n " , read_type_ ? " bulk read" : " sync read" );
314310 if (read_type_ == SYNC) {
@@ -411,13 +407,10 @@ DxlError Dynamixel::SetDxlWriteItems(
411407
412408 return DxlError::OK;
413409}
410+
414411DxlError Dynamixel::SetMultiDxlWrite ()
415412{
416- if (write_data_list_.size () < 2 ) {
417- write_type_ = SYNC;
418- } else {
419- write_type_ = checkWriteType ();
420- }
413+ write_type_ = checkWriteType ();
421414
422415 fprintf (stderr, " Dynamixel Write Type : %s\n " , write_type_ ? " bulk write" : " sync write" );
423416 if (write_type_ == SYNC) {
@@ -447,12 +440,10 @@ DxlError Dynamixel::SetMultiDxlWrite()
447440 }
448441
449442 if (write_type_ == SYNC) {
450- SetSyncWriteItemAndHandler ();
443+ return SetSyncWriteItemAndHandler ();
451444 } else {
452- SetBulkWriteItemAndHandler ();
445+ return SetBulkWriteItemAndHandler ();
453446 }
454-
455- return DxlError::OK;
456447}
457448
458449DxlError Dynamixel::DynamixelEnable (std::vector<uint8_t > id_arr)
@@ -873,6 +864,12 @@ DxlError Dynamixel::WriteMultiDxlData()
873864
874865bool Dynamixel::checkReadType ()
875866{
867+ if (read_data_list_.size () == 1 ) {
868+ if (CheckIndirectReadAvailable (read_data_list_.at (0 ).comm_id ) != DxlError::OK) {
869+ return BULK;
870+ }
871+ }
872+
876873 for (size_t dxl_index = 1 ; dxl_index < read_data_list_.size (); dxl_index++) {
877874 // Check if Indirect Data Read address and size are different
878875 uint16_t indirect_addr[2 ]; // [i-1], [i]
@@ -919,6 +916,12 @@ bool Dynamixel::checkReadType()
919916
920917bool Dynamixel::checkWriteType ()
921918{
919+ if (write_data_list_.size () == 1 ) {
920+ if (CheckIndirectWriteAvailable (write_data_list_.at (0 ).comm_id ) != DxlError::OK) {
921+ return BULK;
922+ }
923+ }
924+
922925 for (size_t dxl_index = 1 ; dxl_index < write_data_list_.size (); dxl_index++) {
923926 // Check if Indirect Data Write address and size are different
924927 uint16_t indirect_addr[2 ]; // [i-1], [i]
0 commit comments