We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 5f68a45 commit 4ec3a97Copy full SHA for 4ec3a97
CHANGELOG.md
@@ -2,6 +2,14 @@
2
3
Full documentation for HIP is available at [docs.amd.com](https://docs.amd.com/)
4
5
+## HIP 6.2 (For ROCm 6.2)
6
+
7
+### Added
8
+- Introduced the `_sync()` version of crosslane builtins such as `shfl_sync()`, `__all_sync()`
9
+ and `__any_sync()`. These take a 64-bit integer as an explicit mask argument.
10
+ - In HIP 6.2, these are hidden behind the preprocessor macro
11
+ `HIP_ENABLE_WARP_SYNC_BUILTINS`, and will be enabled unconditionally in HIP 6.3.
12
13
## HIP 6.1 (For ROCm 6.1)
14
### Optimizations
15
0 commit comments