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merge main into amd-staging (llvm#1989)
2 parents 25e12af + 636b278 commit 16b4168

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‎clang/include/clang/Basic/BuiltinsRISCVXCV.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,8 @@ let Attributes = [NoThrow, Const] in {
2121
//===----------------------------------------------------------------------===//
2222
// XCValu extension.
2323
//===----------------------------------------------------------------------===//
24-
def alu_slet : RISCVXCVBuiltin<"int(int, int)", "xcvalu">;
25-
def alu_sletu : RISCVXCVBuiltin<"int(unsigned int, unsigned int)", "xcvalu">;
24+
def alu_sle : RISCVXCVBuiltin<"int(int, int)", "xcvalu">;
25+
def alu_sleu : RISCVXCVBuiltin<"int(unsigned int, unsigned int)", "xcvalu">;
2626
def alu_exths : RISCVXCVBuiltin<"int(int)", "xcvalu">;
2727
def alu_exthz : RISCVXCVBuiltin<"unsigned int(unsigned int)", "xcvalu">;
2828
def alu_extbs : RISCVXCVBuiltin<"int(int)", "xcvalu">;

‎clang/lib/CodeGen/TargetBuiltins/RISCV.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -388,10 +388,10 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
388388
case RISCV::BI__builtin_riscv_cv_alu_exthz:
389389
return Builder.CreateZExt(Builder.CreateTrunc(Ops[0], Int16Ty), Int32Ty,
390390
"exthz");
391-
case RISCV::BI__builtin_riscv_cv_alu_slet:
391+
case RISCV::BI__builtin_riscv_cv_alu_sle:
392392
return Builder.CreateZExt(Builder.CreateICmpSLE(Ops[0], Ops[1]), Int32Ty,
393393
"sle");
394-
case RISCV::BI__builtin_riscv_cv_alu_sletu:
394+
case RISCV::BI__builtin_riscv_cv_alu_sleu:
395395
return Builder.CreateZExt(Builder.CreateICmpULE(Ops[0], Ops[1]), Int32Ty,
396396
"sleu");
397397
case RISCV::BI__builtin_riscv_cv_alu_subN:

‎clang/lib/Headers/riscv_corev_alu.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -24,13 +24,13 @@ static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_abs(long a) {
2424
return __builtin_abs(a);
2525
}
2626

27-
static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_alu_slet(long a, long b) {
28-
return __builtin_riscv_cv_alu_slet(a, b);
27+
static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_alu_sle(long a, long b) {
28+
return __builtin_riscv_cv_alu_sle(a, b);
2929
}
3030

3131
static __inline__ long __DEFAULT_FN_ATTRS
32-
__riscv_cv_alu_sletu(unsigned long a, unsigned long b) {
33-
return __builtin_riscv_cv_alu_sletu(a, b);
32+
__riscv_cv_alu_sleu(unsigned long a, unsigned long b) {
33+
return __builtin_riscv_cv_alu_sleu(a, b);
3434
}
3535

3636
static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_alu_min(long a, long b) {

‎clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
#include <stdint.h>
66
#include <riscv_corev_alu.h>
77

8-
// CHECK-LABEL: @test_alu_slet(
8+
// CHECK-LABEL: @test_alu_sle(
99
// CHECK-NEXT: entry:
1010
// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i32, align 4
1111
// CHECK-NEXT: [[B_ADDR_I:%.*]] = alloca i32, align 4
@@ -23,11 +23,11 @@
2323
// CHECK-NEXT: [[SLE_I:%.*]] = zext i1 [[TMP4]] to i32
2424
// CHECK-NEXT: ret i32 [[SLE_I]]
2525
//
26-
int test_alu_slet(int32_t a, int32_t b) {
27-
return __riscv_cv_alu_slet(a, b);
26+
int test_alu_sle(int32_t a, int32_t b) {
27+
return __riscv_cv_alu_sle(a, b);
2828
}
2929

30-
// CHECK-LABEL: @test_alu_sletu(
30+
// CHECK-LABEL: @test_alu_sleu(
3131
// CHECK-NEXT: entry:
3232
// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i32, align 4
3333
// CHECK-NEXT: [[B_ADDR_I:%.*]] = alloca i32, align 4
@@ -45,8 +45,8 @@ int test_alu_slet(int32_t a, int32_t b) {
4545
// CHECK-NEXT: [[SLEU_I:%.*]] = zext i1 [[TMP4]] to i32
4646
// CHECK-NEXT: ret i32 [[SLEU_I]]
4747
//
48-
int test_alu_sletu(uint32_t a, uint32_t b) {
49-
return __riscv_cv_alu_sletu(a, b);
48+
int test_alu_sleu(uint32_t a, uint32_t b) {
49+
return __riscv_cv_alu_sleu(a, b);
5050
}
5151

5252
// CHECK-LABEL: @test_alu_min(

‎clang/test/CodeGen/RISCV/riscv-xcvalu.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ int test_abs(int a) {
1616
return __builtin_abs(a);
1717
}
1818

19-
// CHECK-LABEL: @test_alu_slet(
19+
// CHECK-LABEL: @test_alu_sle(
2020
// CHECK-NEXT: entry:
2121
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2222
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
@@ -28,11 +28,11 @@ int test_abs(int a) {
2828
// CHECK-NEXT: [[SLE:%.*]] = zext i1 [[TMP2]] to i32
2929
// CHECK-NEXT: ret i32 [[SLE]]
3030
//
31-
int test_alu_slet(int32_t a, int32_t b) {
32-
return __builtin_riscv_cv_alu_slet(a, b);
31+
int test_alu_sle(int32_t a, int32_t b) {
32+
return __builtin_riscv_cv_alu_sle(a, b);
3333
}
3434

35-
// CHECK-LABEL: @test_alu_sletu(
35+
// CHECK-LABEL: @test_alu_sleu(
3636
// CHECK-NEXT: entry:
3737
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3838
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
@@ -44,8 +44,8 @@ int test_alu_slet(int32_t a, int32_t b) {
4444
// CHECK-NEXT: [[SLEU:%.*]] = zext i1 [[TMP2]] to i32
4545
// CHECK-NEXT: ret i32 [[SLEU]]
4646
//
47-
int test_alu_sletu(uint32_t a, uint32_t b) {
48-
return __builtin_riscv_cv_alu_sletu(a, b);
47+
int test_alu_sleu(uint32_t a, uint32_t b) {
48+
return __builtin_riscv_cv_alu_sleu(a, b);
4949
}
5050

5151
// CHECK-LABEL: @test_alu_exths(

‎clang/test/Driver/print-enabled-extensions/riscv-sifive-p870.c

Lines changed: 81 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,81 @@
1+
// RUN: %clang --target=riscv64 -mcpu=sifive-p870 --print-enabled-extensions | FileCheck %s
2+
// REQUIRES: riscv-registered-target
3+
4+
// CHECK: Extensions enabled for the given RISC-V target
5+
// CHECK-EMPTY:
6+
// CHECK-NEXT: Name Version Description
7+
// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
8+
// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
9+
// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
10+
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
11+
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
12+
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
13+
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
14+
// CHECK-NEXT: v 1.0 'V' (Vector Extension for Application Processors)
15+
// CHECK-NEXT: zic64b 1.0 'Zic64b' (Cache Block Size Is 64 Bytes)
16+
// CHECK-NEXT: zicbom 1.0 'Zicbom' (Cache-Block Management Instructions)
17+
// CHECK-NEXT: zicbop 1.0 'Zicbop' (Cache-Block Prefetch Instructions)
18+
// CHECK-NEXT: zicboz 1.0 'Zicboz' (Cache-Block Zero Instructions)
19+
// CHECK-NEXT: ziccamoa 1.0 'Ziccamoa' (Main Memory Supports All Atomics in A)
20+
// CHECK-NEXT: ziccif 1.0 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)
21+
// CHECK-NEXT: zicclsm 1.0 'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)
22+
// CHECK-NEXT: ziccrse 1.0 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)
23+
// CHECK-NEXT: zicntr 2.0 'Zicntr' (Base Counters and Timers)
24+
// CHECK-NEXT: zicond 1.0 'Zicond' (Integer Conditional Operations)
25+
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
26+
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
27+
// CHECK-NEXT: zihintntl 1.0 'Zihintntl' (Non-Temporal Locality Hints)
28+
// CHECK-NEXT: zihintpause 2.0 'Zihintpause' (Pause Hint)
29+
// CHECK-NEXT: zihpm 2.0 'Zihpm' (Hardware Performance Counters)
30+
// CHECK-NEXT: zimop 1.0 'Zimop' (May-Be-Operations)
31+
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
32+
// CHECK-NEXT: za64rs 1.0 'Za64rs' (Reservation Set Size of at Most 64 Bytes)
33+
// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
34+
// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
35+
// CHECK-NEXT: zama16b 1.0 'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)
36+
// CHECK-NEXT: zawrs 1.0 'Zawrs' (Wait on Reservation Set)
37+
// CHECK-NEXT: zfa 1.0 'Zfa' (Additional Floating-Point)
38+
// CHECK-NEXT: zfbfmin 1.0 'Zfbfmin' (Scalar BF16 Converts)
39+
// CHECK-NEXT: zfh 1.0 'Zfh' (Half-Precision Floating-Point)
40+
// CHECK-NEXT: zfhmin 1.0 'Zfhmin' (Half-Precision Floating-Point Minimal)
41+
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
42+
// CHECK-NEXT: zcb 1.0 'Zcb' (Compressed basic bit manipulation instructions)
43+
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
44+
// CHECK-NEXT: zcmop 1.0 'Zcmop' (Compressed May-Be-Operations)
45+
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
46+
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
47+
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
48+
// CHECK-NEXT: zkr 1.0 'Zkr' (Entropy Source Extension)
49+
// CHECK-NEXT: zkt 1.0 'Zkt' (Data Independent Execution Latency)
50+
// CHECK-NEXT: zvbb 1.0 'Zvbb' (Vector basic bit-manipulation instructions)
51+
// CHECK-NEXT: zvbc 1.0 'Zvbc' (Vector Carryless Multiplication)
52+
// CHECK-NEXT: zve32f 1.0 'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension)
53+
// CHECK-NEXT: zve32x 1.0 'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW)
54+
// CHECK-NEXT: zve64d 1.0 'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension)
55+
// CHECK-NEXT: zve64f 1.0 'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension)
56+
// CHECK-NEXT: zve64x 1.0 'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW)
57+
// CHECK-NEXT: zvfbfmin 1.0 'Zvfbfmin' (Vector BF16 Converts)
58+
// CHECK-NEXT: zvfbfwma 1.0 'Zvfbfwma' (Vector BF16 widening mul-add)
59+
// CHECK-NEXT: zvfh 1.0 'Zvfh' (Vector Half-Precision Floating-Point)
60+
// CHECK-NEXT: zvfhmin 1.0 'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)
61+
// CHECK-NEXT: zvkb 1.0 'Zvkb' (Vector Bit-manipulation used in Cryptography)
62+
// CHECK-NEXT: zvkg 1.0 'Zvkg' (Vector GCM instructions for Cryptography)
63+
// CHECK-NEXT: zvkn 1.0 'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt')
64+
// CHECK-NEXT: zvknc 1.0 'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')
65+
// CHECK-NEXT: zvkned 1.0 'Zvkned' (Vector AES Encryption & Decryption (Single Round))
66+
// CHECK-NEXT: zvkng 1.0 'Zvkng' (shorthand for 'Zvkn' and 'Zvkg')
67+
// CHECK-NEXT: zvknhb 1.0 'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))
68+
// CHECK-NEXT: zvks 1.0 'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt')
69+
// CHECK-NEXT: zvksc 1.0 'Zvksc' (shorthand for 'Zvks' and 'Zvbc')
70+
// CHECK-NEXT: zvksed 1.0 'Zvksed' (SM4 Block Cipher Instructions)
71+
// CHECK-NEXT: zvksg 1.0 'Zvksg' (shorthand for 'Zvks' and 'Zvkg')
72+
// CHECK-NEXT: zvksh 1.0 'Zvksh' (SM3 Hash Function Instructions)
73+
// CHECK-NEXT: zvkt 1.0 'Zvkt' (Vector Data-Independent Execution Latency)
74+
// CHECK-NEXT: zvl128b 1.0 'Zvl128b' (Minimum Vector Length 128)
75+
// CHECK-NEXT: zvl32b 1.0 'Zvl32b' (Minimum Vector Length 32)
76+
// CHECK-NEXT: zvl64b 1.0 'Zvl64b' (Minimum Vector Length 64)
77+
// CHECK-NEXT: supm 1.0 'Supm' (Indicates User-mode Pointer Masking)
78+
// CHECK-EMPTY:
79+
// CHECK-NEXT: Experimental extensions
80+
// CHECK-EMPTY:
81+
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zama16b1p0_zawrs1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkr1p0_zkt1p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvfbfwma1p0_zvfh1p0_zvfhmin1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_supm1p0

‎clang/test/Driver/riscv-cpus.c

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -567,6 +567,11 @@
567567
// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkt"
568568
// MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d"
569569

570+
// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p870 | FileCheck -check-prefix=MCPU-SIFIVE-P870 %s
571+
// MCPU-SIFIVE-P870: "-target-cpu" "sifive-p870"
572+
// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-sifive-p870.c`
573+
// MCPU-SIFIVE-P870-SAME: "-target-abi" "lp64d"
574+
570575
// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=rp2350-hazard3 | FileCheck -check-prefix=MCPU-HAZARD3 %s
571576
// MCPU-HAZARD3: "-target-cpu" "rp2350-hazard3"
572577
// MCPU-HAZARD3-SAME: "-target-feature" "+m"

‎clang/test/Misc/target-invalid-cpu-note/riscv.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,7 @@
3535
// RISCV64-SAME: {{^}}, sifive-p470
3636
// RISCV64-SAME: {{^}}, sifive-p550
3737
// RISCV64-SAME: {{^}}, sifive-p670
38+
// RISCV64-SAME: {{^}}, sifive-p870
3839
// RISCV64-SAME: {{^}}, sifive-s21
3940
// RISCV64-SAME: {{^}}, sifive-s51
4041
// RISCV64-SAME: {{^}}, sifive-s54
@@ -90,6 +91,7 @@
9091
// TUNE-RISCV64-SAME: {{^}}, sifive-p470
9192
// TUNE-RISCV64-SAME: {{^}}, sifive-p550
9293
// TUNE-RISCV64-SAME: {{^}}, sifive-p670
94+
// TUNE-RISCV64-SAME: {{^}}, sifive-p870
9395
// TUNE-RISCV64-SAME: {{^}}, sifive-s21
9496
// TUNE-RISCV64-SAME: {{^}}, sifive-s51
9597
// TUNE-RISCV64-SAME: {{^}}, sifive-s54

‎lldb/include/lldb/Core/FormatEntity.h

Lines changed: 19 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -11,10 +11,10 @@
1111

1212
#include "lldb/lldb-enumerations.h"
1313
#include "lldb/lldb-types.h"
14+
#include "llvm/ADT/SmallVector.h"
1415
#include <algorithm>
1516
#include <cstddef>
1617
#include <cstdint>
17-
1818
#include <string>
1919
#include <vector>
2020

@@ -158,9 +158,7 @@ struct Entry {
158158
}
159159

160160
Entry(Type t = Type::Invalid, const char *s = nullptr,
161-
const char *f = nullptr)
162-
: string(s ? s : ""), printf_format(f ? f : ""), type(t) {}
163-
161+
const char *f = nullptr);
164162
Entry(llvm::StringRef s);
165163
Entry(char ch);
166164

@@ -170,15 +168,19 @@ struct Entry {
170168

171169
void AppendText(const char *cstr);
172170

173-
void AppendEntry(const Entry &&entry) { children.push_back(entry); }
171+
void AppendEntry(const Entry &&entry);
172+
173+
void StartAlternative();
174174

175175
void Clear() {
176176
string.clear();
177177
printf_format.clear();
178-
children.clear();
178+
children_stack.clear();
179+
children_stack.emplace_back();
179180
type = Type::Invalid;
180181
fmt = lldb::eFormatDefault;
181182
number = 0;
183+
level = 0;
182184
deref = false;
183185
}
184186

@@ -191,7 +193,7 @@ struct Entry {
191193
return false;
192194
if (printf_format != rhs.printf_format)
193195
return false;
194-
if (children != rhs.children)
196+
if (children_stack != rhs.children_stack)
195197
return false;
196198
if (type != rhs.type)
197199
return false;
@@ -202,9 +204,18 @@ struct Entry {
202204
return true;
203205
}
204206

207+
std::vector<Entry> &GetChildren();
208+
205209
std::string string;
206210
std::string printf_format;
207-
std::vector<Entry> children;
211+
212+
/// A stack of children entries, used by Scope entries to provide alterantive
213+
/// children. All other entries have a stack of size 1.
214+
/// @{
215+
llvm::SmallVector<std::vector<Entry>, 1> children_stack;
216+
size_t level = 0;
217+
/// @}
218+
208219
Type type;
209220
lldb::Format fmt = lldb::eFormatDefault;
210221
lldb::addr_t number = 0;

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