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Commit 3e32b36

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HuangboNo2HuangboNo2
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1 parent b8db37f commit 3e32b36

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3 files changed

+49
-49
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3 files changed

+49
-49
lines changed

‎bsp/ti-tms320c6678/common/common.c‎

Lines changed: 34 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -10,9 +10,9 @@
1010

1111
#include "common.h"
1212

13-
CSL_BootcfgRegs * gpBootCfgRegs = (CSL_BootcfgRegs *)CSL_BOOT_CFG_REGS;
14-
CSL_CgemRegs * gpCGEM_regs = (CSL_CgemRegs *)CSL_CGEM0_5_REG_BASE_ADDRESS_REGS;
15-
CSL_TmrPlusRegs * gpTimerRegs[9] = {
13+
CSL_BootcfgRegs * gp_bootcfg_regs = (CSL_BootcfgRegs *)CSL_BOOT_CFG_REGS;
14+
CSL_CgemRegs * gp_cgem_regs = (CSL_CgemRegs *)CSL_CGEM0_5_REG_BASE_ADDRESS_REGS;
15+
CSL_TmrPlusRegs * gp_timer_regs[9] = {
1616
(CSL_TmrPlusRegs *)CSL_TIMER_0_REGS,
1717
(CSL_TmrPlusRegs *)CSL_TIMER_1_REGS,
1818
(CSL_TmrPlusRegs *)CSL_TIMER_2_REGS,
@@ -29,22 +29,22 @@ void cpu_interrupt_init(void)
2929
//clear interrupt and excpetion events
3030
ICR = IFR;
3131
ECR = EFR;
32-
IER= 3; //disable all interrupts
32+
IER = 3; //disable all interrupts
3333

3434
/* disable event combine */
35-
gpCGEM_regs->EVTMASK[0] = 0xffffffff;
36-
gpCGEM_regs->EVTMASK[1] = 0xffffffff;
37-
gpCGEM_regs->EVTMASK[2] = 0xffffffff;
38-
gpCGEM_regs->EVTMASK[3] = 0xffffffff;
35+
gp_cgem_regs->EVTMASK[0] = 0xffffffff;
36+
gp_cgem_regs->EVTMASK[1] = 0xffffffff;
37+
gp_cgem_regs->EVTMASK[2] = 0xffffffff;
38+
gp_cgem_regs->EVTMASK[3] = 0xffffffff;
3939

4040
/*Clear all CPU events*/
41-
gpCGEM_regs->EVTCLR[0]= 0xFFFFFFFF;
42-
gpCGEM_regs->EVTCLR[1]= 0xFFFFFFFF;
43-
gpCGEM_regs->EVTCLR[2]= 0xFFFFFFFF;
44-
gpCGEM_regs->EVTCLR[3]= 0xFFFFFFFF;
41+
gp_cgem_regs->EVTCLR[0] = 0xFFFFFFFF;
42+
gp_cgem_regs->EVTCLR[1] = 0xFFFFFFFF;
43+
gp_cgem_regs->EVTCLR[2] = 0xFFFFFFFF;
44+
gp_cgem_regs->EVTCLR[3] = 0xFFFFFFFF;
4545

4646
/*Interrupt Service Table Pointer to begining of LL2 memory*/
47-
ISTP= 0x800000;
47+
ISTP = 0x800000;
4848
}
4949

5050
void keystone_cpu_init(void)
@@ -56,19 +56,19 @@ void keystone_cpu_init(void)
5656
/*===============================Timer=================================*/
5757
void reset_timer(int timer_num)
5858
{
59-
if(gpTimerRegs[timer_num]->TGCR)
59+
if(gp_timer_regs[timer_num]->TGCR)
6060
{
61-
gpTimerRegs[timer_num]->TGCR = 0;
62-
gpTimerRegs[timer_num]->TCR= 0;
61+
gp_timer_regs[timer_num]->TGCR = 0;
62+
gp_timer_regs[timer_num]->TCR= 0;
6363
}
6464
}
6565

6666
void timer64_init(Timer64_Config * tmrCfg)
6767
{
6868
reset_timer(tmrCfg->timer_num);
6969

70-
gpTimerRegs[tmrCfg->timer_num]->CNTLO = 0;
71-
gpTimerRegs[tmrCfg->timer_num]->CNTHI = 0;
70+
gp_timer_regs[tmrCfg->timer_num]->CNTLO = 0;
71+
gp_timer_regs[tmrCfg->timer_num]->CNTHI = 0;
7272

7373
/*please note, in clock mode, two timer periods generate a clock,
7474
one timer period output high voltage level, the other timer period
@@ -80,17 +80,17 @@ void timer64_init(Timer64_Config * tmrCfg)
8080
}
8181

8282
/*the value written into period register is the expected value minus one*/
83-
gpTimerRegs[tmrCfg->timer_num]->PRDLO = _loll(tmrCfg->period-1);
84-
gpTimerRegs[tmrCfg->timer_num]->PRDHI = _hill(tmrCfg->period-1);
83+
gp_timer_regs[tmrCfg->timer_num]->PRDLO = _loll(tmrCfg->period-1);
84+
gp_timer_regs[tmrCfg->timer_num]->PRDHI = _hill(tmrCfg->period-1);
8585
if(tmrCfg->reload_period>1)
8686
{
87-
gpTimerRegs[tmrCfg->timer_num]->RELLO = _loll(tmrCfg->reload_period-1);
88-
gpTimerRegs[tmrCfg->timer_num]->RELHI = _hill(tmrCfg->reload_period-1);
87+
gp_timer_regs[tmrCfg->timer_num]->RELLO = _loll(tmrCfg->reload_period-1);
88+
gp_timer_regs[tmrCfg->timer_num]->RELHI = _hill(tmrCfg->reload_period-1);
8989
}
9090

9191
if(TIMER_WATCH_DOG == tmrCfg->timerMode)
9292
{
93-
gpTimerRegs[tmrCfg->timer_num]->TGCR =
93+
gp_timer_regs[tmrCfg->timer_num]->TGCR =
9494
/*Select watch-dog mode*/
9595
(CSL_TMR_TIMMODE_WDT << CSL_TMR_TGCR_TIMMODE_SHIFT)
9696
/*Remove the timer from reset*/
@@ -99,18 +99,18 @@ void timer64_init(Timer64_Config * tmrCfg)
9999
}
100100
else if(TIMER_PERIODIC_WAVE == tmrCfg->timerMode)
101101
{
102-
gpTimerRegs[tmrCfg->timer_num]->TGCR = TMR_TGCR_PLUSEN_MASK
102+
gp_timer_regs[tmrCfg->timer_num]->TGCR = TMR_TGCR_PLUSEN_MASK
103103
/*for plus featuers, dual 32-bit unchained timer mode should be used*/
104104
| (CSL_TMR_TIMMODE_DUAL_UNCHAINED << CSL_TMR_TGCR_TIMMODE_SHIFT)
105105
/*Remove the timer from reset*/
106106
| (CSL_TMR_TGCR_TIMLORS_MASK);
107107

108108
//in plus mode, interrupt/event must be enabled manually
109-
gpTimerRegs[tmrCfg->timer_num]->INTCTL_STAT= TMR_INTCTLSTAT_EN_ALL_CLR_ALL;
109+
gp_timer_regs[tmrCfg->timer_num]->INTCTL_STAT= TMR_INTCTLSTAT_EN_ALL_CLR_ALL;
110110
}
111111
else
112112
{
113-
gpTimerRegs[tmrCfg->timer_num]->TGCR =
113+
gp_timer_regs[tmrCfg->timer_num]->TGCR =
114114
/*Select 64-bit general timer mode*/
115115
(CSL_TMR_TIMMODE_GPT << CSL_TMR_TGCR_TIMMODE_SHIFT)
116116
/*Remove the timer from reset*/
@@ -119,16 +119,16 @@ void timer64_init(Timer64_Config * tmrCfg)
119119
}
120120

121121
/*make timer stop with emulation*/
122-
gpTimerRegs[tmrCfg->timer_num]->EMUMGT_CLKSPD = (gpTimerRegs[tmrCfg->timer_num]->EMUMGT_CLKSPD&
122+
gp_timer_regs[tmrCfg->timer_num]->EMUMGT_CLKSPD = (gp_timer_regs[tmrCfg->timer_num]->EMUMGT_CLKSPD&
123123
~(CSL_TMR_EMUMGT_CLKSPD_FREE_MASK|CSL_TMR_EMUMGT_CLKSPD_SOFT_MASK));
124124

125125
if(TIMER_WATCH_DOG == tmrCfg->timerMode)
126126
{
127127
/*enable watchdog timer*/
128-
gpTimerRegs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
128+
gp_timer_regs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
129129
| (CSL_TMR_WDTCR_WDKEY_CMD1 << CSL_TMR_WDTCR_WDKEY_SHIFT);
130130

131-
gpTimerRegs[tmrCfg->timer_num]->TCR=
131+
gp_timer_regs[tmrCfg->timer_num]->TCR =
132132
(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
133133
| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
134134
/*The timer is enabled continuously*/
@@ -141,12 +141,12 @@ void timer64_init(Timer64_Config * tmrCfg)
141141
| (0 << CSL_TMR_TCR_TSTAT_LO_SHIFT);
142142

143143
/*active watchdog timer*/
144-
gpTimerRegs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
144+
gp_timer_regs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
145145
| (CSL_TMR_WDTCR_WDKEY_CMD2 << CSL_TMR_WDTCR_WDKEY_SHIFT);
146146
}
147147
else if(TIMER_ONE_SHOT_PULSE == tmrCfg->timerMode)
148148
{
149-
gpTimerRegs[tmrCfg->timer_num]->TCR =
149+
gp_timer_regs[tmrCfg->timer_num]->TCR =
150150
(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
151151
| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
152152
/*The timer is enabled one-shot*/
@@ -160,7 +160,7 @@ void timer64_init(Timer64_Config * tmrCfg)
160160
}
161161
else if(TIMER_PERIODIC_CLOCK == tmrCfg->timerMode)
162162
{
163-
gpTimerRegs[tmrCfg->timer_num]->TCR =
163+
gp_timer_regs[tmrCfg->timer_num]->TCR =
164164
(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
165165
| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
166166
/*The timer is enabled continuously*/
@@ -174,7 +174,7 @@ void timer64_init(Timer64_Config * tmrCfg)
174174
}
175175
else if(TIMER_PERIODIC_WAVE == tmrCfg->timerMode)
176176
{
177-
gpTimerRegs[tmrCfg->timer_num]->TCR =
177+
gp_timer_regs[tmrCfg->timer_num]->TCR =
178178
(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
179179
| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
180180
/*The timer is enabled continuously with period reload*/
@@ -188,7 +188,7 @@ void timer64_init(Timer64_Config * tmrCfg)
188188
}
189189
else /*TIMER_PERIODIC_PULSE*/
190190
{
191-
gpTimerRegs[tmrCfg->timer_num]->TCR =
191+
gp_timer_regs[tmrCfg->timer_num]->TCR =
192192
(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
193193
| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
194194
/*The timer is enabled continuously*/

‎bsp/ti-tms320c6678/common/common.h‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,8 @@
2121
/* DSP core clock speed in Hz */
2222
#define DSP_CORE_SPEED_HZ 1000000000
2323

24-
extern CSL_CgemRegs * gpCGEM_regs;
25-
extern CSL_BootcfgRegs * gpBootCfgRegs;
24+
extern CSL_CgemRegs * gp_cgem_regs;
25+
extern CSL_BootcfgRegs * gp_bootcfg_regs;
2626

2727
/*----------------------Timer plus registers definition----------------*/
2828
typedef struct {
@@ -69,16 +69,16 @@ typedef struct {
6969

7070
#define CSL_TMR_ENAMODE_CONT_RELOAD 3
7171

72-
extern CSL_TmrPlusRegs * gpTimer0Regs;
73-
extern CSL_TmrPlusRegs * gpTimer1Regs;
74-
extern CSL_TmrPlusRegs * gpTimer2Regs;
75-
extern CSL_TmrPlusRegs * gpTimer3Regs;
76-
extern CSL_TmrPlusRegs * gpTimer4Regs;
77-
extern CSL_TmrPlusRegs * gpTimer5Regs;
78-
extern CSL_TmrPlusRegs * gpTimer6Regs;
79-
extern CSL_TmrPlusRegs * gpTimer7Regs;
80-
extern CSL_TmrPlusRegs * gpTimer8Regs;
81-
extern CSL_TmrPlusRegs * gpTimerRegs[];
72+
extern CSL_TmrPlusRegs * gp_timer0_regs;
73+
extern CSL_TmrPlusRegs * gp_timer1_regs;
74+
extern CSL_TmrPlusRegs * gp_timer2_regs;
75+
extern CSL_TmrPlusRegs * gp_timer3_regs;
76+
extern CSL_TmrPlusRegs * gp_timer4_regs;
77+
extern CSL_TmrPlusRegs * gp_timer5_regs;
78+
extern CSL_TmrPlusRegs * gp_timer6_regs;
79+
extern CSL_TmrPlusRegs * gp_timer7_regs;
80+
extern CSL_TmrPlusRegs * gp_timer8_regs;
81+
extern CSL_TmrPlusRegs * gp_timer_regs[];
8282

8383
typedef enum
8484
{

‎bsp/ti-tms320c6678/driver/drv_timer.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ void rt_hw_systick_isr(void)
3636
void rt_hw_system_timer_init(void)
3737
{
3838
// initial system timer interrupt, map local timer interrupt to INT14
39-
gpCGEM_regs->INTMUX3 = (CSL_GEM_TINTLN << CSL_CGEM_INTMUX3_INTSEL14_SHIFT);
39+
gp_cgem_regs->INTMUX3 = (CSL_GEM_TINTLN << CSL_CGEM_INTMUX3_INTSEL14_SHIFT);
4040
// enable CPU INT14
4141
rt_hw_interrupt_umask(1 << 14);
4242

@@ -45,15 +45,15 @@ void rt_hw_system_timer_init(void)
4545

4646
/**
4747
* The function initial system timer.
48-
* Use local timer (==DNUM of a core) to generate a clock on TIMO0,interrupts are generated as well
48+
* Use local timer (== DNUM of a core) to generate a clock on TIMO0,interrupts are generated as well
4949
*
5050
*/
5151
void rt_hw_system_timer_start(void)
5252
{
5353
Timer64_Config tmrCfg;
5454

5555
// select output on TIMO0 from local timer.
56-
gpBootCfgRegs->TOUTSEL = (DNUM*2) << CSL_BOOTCFG_TOUTSEL_TOUTSEL0_SHIFT;
56+
gp_bootcfg_regs->TOUTSEL = (DNUM*2) << CSL_BOOTCFG_TOUTSEL_TOUTSEL0_SHIFT;
5757

5858
// configure the timer to generate clocks and interrupts
5959
tmrCfg.timer_num = DNUM;

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