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bsp/nxp/mcx/mcxe: Add ADC driver.
Signed-off-by: Yilin Sun <[email protected]>
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‎bsp/nxp/mcx/mcxe/Libraries/drivers/drv_adc.c‎

Lines changed: 167 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-05-16 shelton first version
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* 2024-07-21 liujianhua added mcxa153
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*
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*/
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#include <rtconfig.h>
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#include <rtdevice.h>
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#include "fsl_adc12.h"
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#include "fsl_pmc.h"
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#define DBG_TAG "drv.adc"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#ifdef RT_USING_ADC
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#define ADC_VBG_CH 27
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#define ADC_VBG_VOLT 1000
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struct mcx_adc
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{
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struct rt_adc_device adc_device;
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ADC_Type *adc_base;
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clock_ip_name_t clock_ip_name;
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clock_ip_src_t clock_ip_src;
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uint8_t resolution_bits;
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uint8_t max_channels;
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uint32_t vref;
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char *name;
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};
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static struct mcx_adc mcx_adc_obj[] =
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{
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#ifdef BSP_USING_ADC0
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{
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.adc_base = ADC0,
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.clock_ip_name = kCLOCK_Adc0,
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.clock_ip_src = kCLOCK_IpSrcSysOscAsync,
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.resolution_bits = 12,
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.max_channels = 32,
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.name = "adc0",
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},
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#endif
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#ifdef BSP_USING_ADC1
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{
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.adc_base = ADC1,
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.clock_ip_name = kCLOCK_Adc1,
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.clock_ip_src = kCLOCK_IpSrcSysOscAsync,
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.resolution_bits = 12,
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.max_channels = 32,
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.name = "adc1",
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},
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#endif
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};
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static uint16_t mcx_adc_get_raw(struct mcx_adc *adc, uint32_t channel)
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{
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adc12_channel_config_t chnl_cfg = {0};
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chnl_cfg.channelNumber = channel;
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chnl_cfg.enableInterruptOnConversionCompleted = false;
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ADC12_SetChannelConfig(adc->adc_base, 0, &chnl_cfg);
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while ((ADC12_GetChannelStatusFlags(adc->adc_base, 0) & kADC12_ChannelConversionCompletedFlag) == 0U)
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{
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}
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return ADC12_GetChannelConversionValue(adc->adc_base, 0);
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}
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static rt_err_t mcx_adc_set_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled)
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{
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RT_ASSERT(device != RT_NULL);
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struct mcx_adc *adc = device->parent.user_data;
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/* ADC is enabled by global probe. */
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RT_UNUSED(adc);
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return RT_EOK;
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}
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static rt_int16_t mcx_get_vref(struct rt_adc_device *device)
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{
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RT_ASSERT(device != RT_NULL);
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struct mcx_adc *adc = device->parent.user_data;
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return (int16_t)adc->vref;
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}
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static rt_err_t mcx_adc_get_value(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value)
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{
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RT_ASSERT(device != RT_NULL);
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struct mcx_adc *adc = device->parent.user_data;
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*value = mcx_adc_get_raw(adc, channel);
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return RT_EOK;
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}
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static rt_uint8_t mcx_adc_get_resolution(struct rt_adc_device *device)
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{
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RT_ASSERT(device != RT_NULL);
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struct mcx_adc *adc = device->parent.user_data;
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return adc->resolution_bits;
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}
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static const struct rt_adc_ops mcx_adc_ops =
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{
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.get_resolution = mcx_adc_get_resolution,
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.enabled = mcx_adc_set_enabled,
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.convert = mcx_adc_get_value,
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.get_vref = mcx_get_vref,
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};
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static int rt_hw_adc_init(void)
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{
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int result = RT_EOK;
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int i = 0;
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for (i = 0; i < sizeof(mcx_adc_obj) / sizeof(mcx_adc_obj[0]); i++)
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{
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struct mcx_adc *adc = &mcx_adc_obj[i];
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CLOCK_SetIpSrc(adc->clock_ip_name, adc->clock_ip_src);
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adc12_config_t cfg;
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ADC12_GetDefaultConfig(&cfg);
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cfg.clockSource = kADC12_ClockSourceAlt0; /* Only available selection. */
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cfg.resolution = kADC12_Resolution12Bit;
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cfg.sampleClockCount = 64;
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ADC12_Init(adc->adc_base, &cfg);
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ADC12_EnableHardwareTrigger(adc->adc_base, false);
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if (ADC12_DoAutoCalibration(adc->adc_base) != kStatus_Success)
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{
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return RT_ERROR;
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}
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uint32_t vref_raw = mcx_adc_get_raw(adc, ADC_VBG_CH);
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adc->vref = (1U << adc->resolution_bits) * ADC_VBG_VOLT / vref_raw;
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if (rt_hw_adc_register(&mcx_adc_obj[i].adc_device, mcx_adc_obj[i].name, &mcx_adc_ops, &mcx_adc_obj[i]) != RT_EOK)
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{
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return RT_ERROR;
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}
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}
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return result;
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}
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INIT_BOARD_EXPORT(rt_hw_adc_init);
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#endif /* BSP_USING_ADC */

‎bsp/nxp/mcx/mcxe/Libraries/drivers/drv_spi.c‎

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -34,11 +34,8 @@ struct mcx_spi_bus
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LPSPI_Type *spi_base;
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clock_ip_name_t clock_ip_name;
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clock_ip_src_t clock_ip_src;
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clock_name_t clock_name;
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rt_sem_t sem;
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char *name;
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rt_sem_t sem;
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char *name;
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};
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static struct mcx_spi_bus mcx_spi_buses[] =
@@ -150,7 +147,7 @@ int rt_hw_spi_init(void)
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masterConfig.lastSckToPcsDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U;
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masterConfig.betweenTransferDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U;
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LPSPI_MasterInit(priv->spi_base, &masterConfig, CLOCK_GetFreq(priv->clock_name));
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LPSPI_MasterInit(priv->spi_base, &masterConfig, CLOCK_GetIpFreq(priv->clock_ip_name));
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rt_spi_bus_register(&priv->spi_bus, priv->name, &lpc_spi_ops);
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}

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