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[libcpu] mips: Merge loongson_1 into gs232
Previously Loongson 1B and Loongson 1C have their own libcpu implemention, but they're almost identical. So we merge them into gs232 and adapt to new common code. Signed-off-by: Jiaxun Yang <[email protected]>
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‎libcpu/mips/loongson_1b/SConscript‎ renamed to ‎libcpu/mips/gs232/SConscript‎

File renamed without changes.

‎libcpu/mips/gs232/cache.c‎

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/*
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* Cache Ops For Loongson GS232
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*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2010-07-09 Bernard first version
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* 2011-08-08 lgnq modified for LS1B
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* 2015-07-08 chinesebear modified for loongson 1c
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*/
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#include <rtthread.h>
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#include <mips.h>
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#define K0BASE 0x80000000
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#define PRID_LS1C 0x4220
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extern void Clear_TagLo (void);
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extern void Invalidate_Icache_Ls1c(unsigned int);
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extern void Invalidate_Dcache_ClearTag_Ls1c(unsigned int);
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extern void Invalidate_Dcache_Fill_Ls1c(unsigned int);
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extern void Writeback_Invalidate_Dcache(unsigned int);
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extern void enable_cpu_cache(void);
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typedef struct cacheinfo_t
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{
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unsigned int icache_size;
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unsigned int dcache_size;
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unsigned int icacheline_size;
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unsigned int dcacheline_size;
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} cacheinfo_t ;
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typedef struct cacheop_t
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{
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void (*Clear_TagLo) (void);
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void (*Invalidate_Icache) (unsigned int);
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void (*Invalidate_Dcache_Fill) (unsigned int);
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void (*Invalidate_Dcache_ClearTag) (unsigned int);
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void (*Init_Cache)(void);
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} cacheop_t ;
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static cacheop_t cacheop, *pcacheop;
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static cacheinfo_t cacheinfo, *pcacheinfo;
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int identify_cpu(void)
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{
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unsigned int cpu_id;
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pcacheop = &cacheop;
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pcacheinfo = &cacheinfo;
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rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
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cpu_id = read_c0_prid();
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switch (cpu_id)
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{
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case PRID_LS1C:
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rt_kprintf("CPU:Loongson 1C\n");
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pcacheop->Clear_TagLo = Clear_TagLo;
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pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1c;
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pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1c;
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pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1c;
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break;
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default:
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rt_kprintf("Unknown CPU type, system halted!\n");
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while (1)
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{
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;
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}
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break;
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}
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return 0;
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}
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void probe_cache(void)
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{
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unsigned int config1 = read_c0_config1();
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unsigned int icache_size, icache_line_size, icache_sets, icache_ways;
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unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways;
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if ((icache_line_size = ((config1 >> 19) & 7)))
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icache_line_size = 2 << icache_line_size;
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else
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icache_line_size = icache_line_size;
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icache_sets = 64 << ((config1 >> 22) & 7);
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icache_ways = 1 + ((config1 >> 16) & 7);
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icache_size = icache_sets * icache_ways * icache_line_size;
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if ((dcache_line_size = ((config1 >> 10) & 7)))
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dcache_line_size = 2 << dcache_line_size;
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else
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dcache_line_size = dcache_line_size;
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dcache_sets = 64 << ((config1 >> 13) & 7);
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dcache_ways = 1 + ((config1 >> 7) & 7);
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dcache_size = dcache_sets * dcache_ways * dcache_line_size;
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rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size);
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rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size);
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pcacheinfo->icache_size = icache_size;
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pcacheinfo->dcache_size = dcache_size;
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pcacheinfo->icacheline_size = icache_line_size;
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pcacheinfo->dcacheline_size = dcache_line_size;
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return ;
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}
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void invalidate_writeback_dcache_all(void)
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{
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unsigned int start = K0BASE;
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unsigned int end = (start + pcacheinfo->dcache_size);
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while (start < end)
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{
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Writeback_Invalidate_Dcache(start); //hit writeback invalidate
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start += pcacheinfo->dcacheline_size;
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}
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}
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void invalidate_writeback_dcache(unsigned long addr, int size)
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{
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unsigned long start, end;
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start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
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end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
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while (start <end)
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{
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Writeback_Invalidate_Dcache(start);
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start += pcacheinfo->dcacheline_size;
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}
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}
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void invalidate_icache_all(void)
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{
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unsigned int start = K0BASE;
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unsigned int end = (start + pcacheinfo->icache_size);
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while (start < end)
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{
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pcacheop->Invalidate_Icache(start);
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start += pcacheinfo->icacheline_size;
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}
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}
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void invalidate_dcache_all(void)
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{
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unsigned int start = K0BASE;
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unsigned int end = (start + pcacheinfo->dcache_size);
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while (start <end)
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{
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Invalidate_Dcache_Fill_Ls1c(start);
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start += pcacheinfo->icacheline_size;
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}
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}
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//with cache disabled
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void init_dcache(void)
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{
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unsigned int start = K0BASE;
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unsigned int end = (start + pcacheinfo->dcache_size);
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while (start < end)
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{
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pcacheop->Invalidate_Dcache_ClearTag(start);
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start += pcacheinfo->dcacheline_size;
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}
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}
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void rt_hw_cache_init(void)
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{
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unsigned int start, end;
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/* 1. identify cpu and probe cache */
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identify_cpu();
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probe_cache();
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start = K0BASE;
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end = (start + pcacheinfo->icache_size);
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/*
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* 2. clear CP0 taglo/taghi register;
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*/
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pcacheop->Clear_TagLo();
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/*
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* 3. invalidate instruction cache;
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*/
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while (start < end)
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{
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pcacheop->Invalidate_Icache(start); //index invalidate icache
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start += pcacheinfo->icacheline_size;
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}
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/*
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* 4. invalidate data cache;
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*/
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start = K0BASE;
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end = (start + pcacheinfo->dcache_size);
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while(start < end)
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{
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pcacheop->Invalidate_Dcache_ClearTag(start);
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start += pcacheinfo->dcacheline_size;
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}
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start = K0BASE;
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while(start < end)
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{
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pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache
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start += pcacheinfo->dcacheline_size;
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}
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start = K0BASE;
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while(start < end)
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{
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pcacheop->Invalidate_Dcache_ClearTag(start);
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start += pcacheinfo->dcacheline_size;
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}
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/* enable cache */
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enable_cpu_cache();
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rt_kprintf("enable cpu cache done\n");
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return ;
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}
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‎libcpu/mips/loongson_1c/cache.h‎ renamed to ‎libcpu/mips/gs232/cache.h‎

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/*
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* File : cache.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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* Cache Ops For Loongson GS232
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*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2010-07-09 Bernard first version
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* 2011-08-08 lgnq modified for LS1B
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* 2010-07-09 Bernard first version
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* 2011-08-08 lgnq modified for LS1B
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* 2015-07-08 chinesebear modified for loongson 1c
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*/
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#ifndef __CACHE_H__
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#define __CACHE_H__
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/*
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* Cache Operations
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*/

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