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@newflydd newflydd commented Jan 9, 2025

拉取/合并请求描述:(PR description)

[

为什么提交这份PR (why to submit this PR)

  • 瑞萨系列HAL_Drivers驱动中rt_pin_get函数无法获取准确的引脚
  • 瑞萨的sci驱动在使用R9A07芯片(EtherKit开发板)时有寄存器错误

你的解决方案是什么 (what is your solution)

  • 修改ra_pin_get函数,规范PIN表达式定义,使用“PXX_X”或“pXX_X”的格式定义PIN引脚
  • 修改ra_uart_putc函数,增加宏判断,并修复R9A07系列芯片的寄存器问题

请提供验证的bsp和config (provide the config and bsp)

  • BSP: bsp/renesas/rzn2l_rsk EtherKit Board
  • .config: 不需要改
  • action:

]

当前拉取/合并请求的状态 Intent for your PR

必须选择一项 Choose one (Mandatory):

  • 本拉取/合并请求是一个草稿版本 This PR is for a code-review and is intended to get feedback
  • 本拉取/合并请求是一个成熟版本 This PR is mature, and ready to be integrated into the repo

代码质量 Code Quality:

我在这个拉取/合并请求中已经考虑了 As part of this pull request, I've considered the following:

  • 已经仔细查看过代码改动的对比 Already check the difference between PR and old code
  • 代码风格正确,包括缩进空格,命名及其他风格 Style guide is adhered to, including spacing, naming and other styles
  • 没有垃圾代码,代码尽量精简,不包含#if 0代码,不包含已经被注释了的代码 All redundant code is removed and cleaned up
  • 所有变更均有原因及合理的,并且不会影响到其他软件组件代码或BSP All modifications are justified and not affect other components or BSP
  • 对难懂代码均提供对应的注释 I've commented appropriately where code is tricky
  • 代码是高质量的 Code in this PR is of high quality
  • 已经使用formatting 等源码格式化工具确保格式符合RT-Thread代码规范 This PR complies with RT-Thread code specification
  • 如果是新增bsp, 已经添加ci检查到.github/workflows/bsp_buildings.yml 详细请参考链接BSP自查

fix `rt_pin_get` function for RENESAS chips, use "PXX_X" or "pXX_X" string format to define a PIN
fix a register problem for R9A07 series chips
@newflydd newflydd requested a review from Rbb666 as a code owner January 9, 2025 07:13
@github-actions github-actions bot added BSP BSP: Renesas BSP related with Renesas labels Jan 9, 2025
newflydd and others added 3 commits January 9, 2025 15:31
@mysterywolf
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pXX_X中xxx可以给个具体例子嘛 另外注释需要用/**/

@newflydd
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pXX_X中xxx可以给个具体例子嘛 另外注释需要用/**/

P18_1

@Rbb666
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Rbb666 commented Jan 10, 2025

这块是否也有在ra平台上验证通过呢?

@newflydd
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这块是否也有在ra平台上验证通过呢?

没有,需要调整,暂时转draft,等我修完。

RA的FSP用的PXXX表达式定义PIN,其中第一个X是PORT,后面两个XX是PIN,也就是PORT1位,PIN2位

RX的FSP用的PXX_X定义PIN,也就是PORT2位,PIN1位

二者不兼容,等我用宏区分一下。

@newflydd newflydd marked this pull request as draft January 10, 2025 02:15
unicornx and others added 5 commits January 10, 2025 17:14
RISCV_S_MODE configuration only affects the code in
libcpu/risc-v/virt64, and the only bsp using this
libcpu is qemu-virt64-riscv.

Considering s-mode is the default mode RT-Thread
running on virt64 machine, it seems unnecessary to
make RISCV_S_MODE a Kconfig option.

Solution: Remove RISCV_S_MODE from Kconfig and define
it as a macro in the code in libcpu/risc-v/virt64.

Plus, due to this macro is only related to virt64, rename
RISCV_S_MODE to RISCV_VIRT64_S_MODE.

Update the .config/rtconfig.h in this patch.

Signed-off-by: Chen Wang <[email protected]>
@github-actions github-actions bot added Kernel PR has src relate code tools Arch: RISC-V BSP related with risc-v libcpu Component labels Jan 13, 2025
@newflydd newflydd marked this pull request as ready for review January 13, 2025 06:01
@newflydd newflydd closed this Jan 13, 2025
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6 participants