force bitfiles to be identical for same source code#2748
force bitfiles to be identical for same source code#2748iceman1001 merged 7 commits intoRfidResearchGroup:masterfrom
Conversation
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You are welcome to add an entry to the CHANGELOG.md as well |
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How about .gitignore and then only certain people would be able to commit the generated fgpa binaries? |
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I don't think the .gitignore really solves the issue - once the bitfile is checked into the repo (which I assume we do want), changes to it subsequently will still be flagged and added by git as usual. If you are suggesting fully not tracking the bitfiles, that would be a solution, although I personally like deterministic bitfiles in any case |
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I guess looking at commits, its not many people who is actually compiling the fpga images. You are an exception. |
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Is it on the |
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It seems like they all have the date string in them - you can check with |
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Actually, now I look at it again, this PR is incorrect - the location of the date string isn't fixed because it depends on the file name 😅 I can fix this if you think the PR has merit, otherwise I'll close it and just use the solution locally; it is fairly minor after all. |
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Ah, you are correct! There is a bit of c which will parse the date/time directly from the bitfile. As a workaround to this, I would propose that the timestamp of the file is used instead. This is ignored by git so still fulfills my original objective. I have pushed an update that would use the file timestamp instead - it works well - let me know what you think? Just as a note: it's not ready to merge yet as I need to fix the bitfile parsing slightly |
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@n-hutton let me know when you feel this PR is ready to merge |
…roxmark3 into deterministic_bitfile_builds2
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I am happy to merge this |


The bitfile generated by
xilinx webpack ISE 10.1was not deterministic - that is, for a given set of input files, the bitfile was always different.This is due to bitgen inserting an ascii string of datetime, at the start of the file. You can see this with xxd.
There is no option to override or disable this, so this solution is just to overwrite that portion of the binary file. This way, you're not constantly committing essentially the same bitfile to the repo again and again.
Place and route is another step that is random and could produce different bitfiles. The fpga is so empty that differing starting seeds produced the same result currently, but I have added a fixed seed so that it will not be a source of differing bitfiles in the future.
I don't know if you used a different version than
Xilinx WebPack ISE 10.1you'd still get a different bitfile initially I think.