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PM / devfreq: rockchip-dfi: Handle LPDDR2 correctly
According to the downstream driver the DDRMON_CTRL_LPDDR23 bit must be set for both LPDDR2 and LPDDR3. Add the missing LPDDR2 case and while at it turn the if/else if/else into switch/case which makes it easier to read. Link: https://lore.kernel.org/all/[email protected]/ Reviewed-by: Jonathan Cameron <[email protected]> Reviewed-by: Sebastian Reichel <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Signed-off-by: Sascha Hauer <[email protected]> Signed-off-by: Chanwoo Choi <[email protected]>
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drivers/devfreq/event/rockchip-dfi.c

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -83,12 +83,19 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
8383
DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL);
8484

8585
/* set ddr type to dfi */
86-
if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3)
86+
switch (dfi->ddr_type) {
87+
case ROCKCHIP_DDRTYPE_LPDDR2:
88+
case ROCKCHIP_DDRTYPE_LPDDR3:
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writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK),
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dfi_regs + DDRMON_CTRL);
89-
else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4)
91+
break;
92+
case ROCKCHIP_DDRTYPE_LPDDR4:
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writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK),
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dfi_regs + DDRMON_CTRL);
95+
break;
96+
default:
97+
break;
98+
}
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93100
/* enable count, use software mode */
94101
writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),

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