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Merge branches 'clk-vc5', 'clk-silabs', 'clk-aspeed', 'clk-qoriq' and 'clk-rohm' into clk-next
 - Support crystal load capacitance for Versaclock VC5 - Add a "skip recall" DT binding for Silicon Labs' si570 to avoid glitches at boot * clk-vc5: clk: vc5: Add support for optional load capacitance dt-bindings: clk: versaclock5: Add optional load capacitance property * clk-silabs: clk: si570: Skip NVM to RAM recall operation if an optional property is set dt-bindings: clock: si570: Add 'silabs,skip-recall' property * clk-aspeed: clk: aspeed: Fix APLL calculate formula from ast2600-A2 * clk-qoriq: clk: qoriq: use macros to generate pll_mask * clk-rohm: clk: BD718x7: Do not depend on parent driver data
6 parents 242d8cf + f3d661d + d9d4944 + 6286ce1 + fa4dd53 + ddddfaf commit 11f8310

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7 files changed

+161
-38
lines changed

7 files changed

+161
-38
lines changed

‎Documentation/devicetree/bindings/clock/idt,versaclock5.yaml

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,12 @@ properties:
5959
minItems: 1
6060
maxItems: 2
6161

62+
idt,xtal-load-femtofarads:
63+
$ref: /schemas/types.yaml#/definitions/uint32
64+
minimum: 9000
65+
maximum: 22760
66+
description: Optional load capacitor for XTAL1 and XTAL2
67+
6268
patternProperties:
6369
"^OUT[1-4]$":
6470
type: object

‎Documentation/devicetree/bindings/clock/silabs,si570.txt

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,8 @@ Optional properties:
2828
- clock-frequency: Output frequency to generate. This defines the output
2929
frequency set during boot. It can be reprogrammed during
3030
runtime through the common clock framework.
31+
- silabs,skip-recall: Do not perform NVM->RAM recall operation. It will rely
32+
on hardware loading of RAM from NVM at power on.
3133

3234
Example:
3335
si570: clock-generator@5d {

‎drivers/clk/clk-ast2600.c

Lines changed: 27 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,8 @@
1717

1818
#define ASPEED_G6_NUM_CLKS 71
1919

20-
#define ASPEED_G6_SILICON_REV 0x004
20+
#define ASPEED_G6_SILICON_REV 0x014
21+
#define CHIP_REVISION_ID GENMASK(23, 16)
2122

2223
#define ASPEED_G6_RESET_CTRL 0x040
2324
#define ASPEED_G6_RESET_CTRL2 0x050
@@ -190,18 +191,34 @@ static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
190191
static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)
191192
{
192193
unsigned int mult, div;
194+
u32 chip_id = readl(scu_g6_base + ASPEED_G6_SILICON_REV);
193195

194-
if (val & BIT(20)) {
195-
/* Pass through mode */
196-
mult = div = 1;
196+
if (((chip_id & CHIP_REVISION_ID) >> 16) >= 2) {
197+
if (val & BIT(24)) {
198+
/* Pass through mode */
199+
mult = div = 1;
200+
} else {
201+
/* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */
202+
u32 m = val & 0x1fff;
203+
u32 n = (val >> 13) & 0x3f;
204+
u32 p = (val >> 19) & 0xf;
205+
206+
mult = (m + 1);
207+
div = (n + 1) * (p + 1);
208+
}
197209
} else {
198-
/* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
199-
u32 m = (val >> 5) & 0x3f;
200-
u32 od = (val >> 4) & 0x1;
201-
u32 n = val & 0xf;
210+
if (val & BIT(20)) {
211+
/* Pass through mode */
212+
mult = div = 1;
213+
} else {
214+
/* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
215+
u32 m = (val >> 5) & 0x3f;
216+
u32 od = (val >> 4) & 0x1;
217+
u32 n = val & 0xf;
202218

203-
mult = (2 - od) * (m + 2);
204-
div = n + 1;
219+
mult = (2 - od) * (m + 2);
220+
div = n + 1;
221+
}
205222
}
206223
return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
207224
mult, div);

‎drivers/clk/clk-bd718x7.c

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -31,12 +31,12 @@ struct bd718xx_clk {
3131
u8 reg;
3232
u8 mask;
3333
struct platform_device *pdev;
34-
struct rohm_regmap_dev *mfd;
34+
struct regmap *regmap;
3535
};
3636

3737
static int bd71837_clk_set(struct bd718xx_clk *c, unsigned int status)
3838
{
39-
return regmap_update_bits(c->mfd->regmap, c->reg, c->mask, status);
39+
return regmap_update_bits(c->regmap, c->reg, c->mask, status);
4040
}
4141

4242
static void bd71837_clk_disable(struct clk_hw *hw)
@@ -62,7 +62,7 @@ static int bd71837_clk_is_enabled(struct clk_hw *hw)
6262
int rval;
6363
struct bd718xx_clk *c = container_of(hw, struct bd718xx_clk, hw);
6464

65-
rval = regmap_read(c->mfd->regmap, c->reg, &enabled);
65+
rval = regmap_read(c->regmap, c->reg, &enabled);
6666

6767
if (rval)
6868
return rval;
@@ -82,7 +82,6 @@ static int bd71837_clk_probe(struct platform_device *pdev)
8282
int rval = -ENOMEM;
8383
const char *parent_clk;
8484
struct device *parent = pdev->dev.parent;
85-
struct rohm_regmap_dev *mfd = dev_get_drvdata(parent);
8685
struct clk_init_data init = {
8786
.name = "bd718xx-32k-out",
8887
.ops = &bd71837_clk_ops,
@@ -93,6 +92,10 @@ static int bd71837_clk_probe(struct platform_device *pdev)
9392
if (!c)
9493
return -ENOMEM;
9594

95+
c->regmap = dev_get_regmap(pdev->dev.parent, NULL);
96+
if (!c->regmap)
97+
return -ENODEV;
98+
9699
init.num_parents = 1;
97100
parent_clk = of_clk_get_parent_name(parent->of_node, 0);
98101

@@ -119,7 +122,6 @@ static int bd71837_clk_probe(struct platform_device *pdev)
119122
dev_err(&pdev->dev, "Unknown clk chip\n");
120123
return -EINVAL;
121124
}
122-
c->mfd = mfd;
123125
c->pdev = pdev;
124126
c->hw.init = &init;
125127

‎drivers/clk/clk-qoriq.c

Lines changed: 43 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/*
33
* Copyright 2013 Freescale Semiconductor, Inc.
4+
* Copyright 2021 NXP
45
*
56
* clock driver for Freescale QorIQ SoCs.
67
*/
@@ -564,7 +565,9 @@ static const struct clockgen_chipinfo chipinfo[] = {
564565
.cmux_to_group = {
565566
0, 1, 1, 1, -1
566567
},
567-
.pll_mask = 0x3f,
568+
.pll_mask = BIT(PLATFORM_PLL) |
569+
BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |
570+
BIT(CGB_PLL1) | BIT(CGB_PLL2),
568571
.flags = CG_PLL_8BIT,
569572
},
570573
{
@@ -580,7 +583,9 @@ static const struct clockgen_chipinfo chipinfo[] = {
580583
.cmux_to_group = {
581584
0, 1, 1, 1, -1
582585
},
583-
.pll_mask = 0x3f,
586+
.pll_mask = BIT(PLATFORM_PLL) |
587+
BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |
588+
BIT(CGB_PLL1) | BIT(CGB_PLL2),
584589
.flags = CG_PLL_8BIT,
585590
},
586591
{
@@ -591,7 +596,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
591596
.cmux_to_group = {
592597
0, -1
593598
},
594-
.pll_mask = 0x03,
599+
.pll_mask = BIT(PLATFORM_PLL) |
600+
BIT(CGA_PLL1) | BIT(CGA_PLL2),
595601
},
596602
{
597603
.compat = "fsl,ls1028a-clockgen",
@@ -605,7 +611,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
605611
.cmux_to_group = {
606612
0, 0, 0, 0, -1
607613
},
608-
.pll_mask = 0x07,
614+
.pll_mask = BIT(PLATFORM_PLL) |
615+
BIT(CGA_PLL1) | BIT(CGA_PLL2),
609616
.flags = CG_VER3 | CG_LITTLE_ENDIAN,
610617
},
611618
{
@@ -620,7 +627,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
620627
.cmux_to_group = {
621628
0, -1
622629
},
623-
.pll_mask = 0x07,
630+
.pll_mask = BIT(PLATFORM_PLL) |
631+
BIT(CGA_PLL1) | BIT(CGA_PLL2),
624632
.flags = CG_PLL_8BIT,
625633
},
626634
{
@@ -635,7 +643,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
635643
.cmux_to_group = {
636644
0, -1
637645
},
638-
.pll_mask = 0x07,
646+
.pll_mask = BIT(PLATFORM_PLL) |
647+
BIT(CGA_PLL1) | BIT(CGA_PLL2),
639648
.flags = CG_PLL_8BIT,
640649
},
641650
{
@@ -649,7 +658,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
649658
.cmux_to_group = {
650659
0, 0, -1
651660
},
652-
.pll_mask = 0x07,
661+
.pll_mask = BIT(PLATFORM_PLL) |
662+
BIT(CGA_PLL1) | BIT(CGA_PLL2),
653663
.flags = CG_VER3 | CG_LITTLE_ENDIAN,
654664
},
655665
{
@@ -660,7 +670,7 @@ static const struct clockgen_chipinfo chipinfo[] = {
660670
.cmux_to_group = {
661671
0, -1
662672
},
663-
.pll_mask = 0x03,
673+
.pll_mask = BIT(PLATFORM_PLL) | BIT(CGA_PLL1),
664674
},
665675
{
666676
.compat = "fsl,ls2080a-clockgen",
@@ -670,7 +680,9 @@ static const struct clockgen_chipinfo chipinfo[] = {
670680
.cmux_to_group = {
671681
0, 0, 1, 1, -1
672682
},
673-
.pll_mask = 0x37,
683+
.pll_mask = BIT(PLATFORM_PLL) |
684+
BIT(CGA_PLL1) | BIT(CGA_PLL2) |
685+
BIT(CGB_PLL1) | BIT(CGB_PLL2),
674686
.flags = CG_VER3 | CG_LITTLE_ENDIAN,
675687
},
676688
{
@@ -681,7 +693,9 @@ static const struct clockgen_chipinfo chipinfo[] = {
681693
.cmux_to_group = {
682694
0, 0, 0, 0, 1, 1, 1, 1, -1
683695
},
684-
.pll_mask = 0x37,
696+
.pll_mask = BIT(PLATFORM_PLL) |
697+
BIT(CGA_PLL1) | BIT(CGA_PLL2) |
698+
BIT(CGB_PLL1) | BIT(CGB_PLL2),
685699
.flags = CG_VER3 | CG_LITTLE_ENDIAN,
686700
},
687701
{
@@ -694,7 +708,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
694708
.cmux_to_group = {
695709
0, 0, 1, 1, -1
696710
},
697-
.pll_mask = 0x07,
711+
.pll_mask = BIT(PLATFORM_PLL) |
712+
BIT(CGA_PLL1) | BIT(CGA_PLL2),
698713
},
699714
{
700715
.compat = "fsl,p3041-clockgen",
@@ -706,7 +721,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
706721
.cmux_to_group = {
707722
0, 0, 1, 1, -1
708723
},
709-
.pll_mask = 0x07,
724+
.pll_mask = BIT(PLATFORM_PLL) |
725+
BIT(CGA_PLL1) | BIT(CGA_PLL2),
710726
},
711727
{
712728
.compat = "fsl,p4080-clockgen",
@@ -718,7 +734,9 @@ static const struct clockgen_chipinfo chipinfo[] = {
718734
.cmux_to_group = {
719735
0, 0, 0, 0, 1, 1, 1, 1, -1
720736
},
721-
.pll_mask = 0x1f,
737+
.pll_mask = BIT(PLATFORM_PLL) |
738+
BIT(CGA_PLL1) | BIT(CGA_PLL2) |
739+
BIT(CGA_PLL3) | BIT(CGA_PLL4),
722740
},
723741
{
724742
.compat = "fsl,p5020-clockgen",
@@ -730,7 +748,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
730748
.cmux_to_group = {
731749
0, 1, -1
732750
},
733-
.pll_mask = 0x07,
751+
.pll_mask = BIT(PLATFORM_PLL) |
752+
BIT(CGA_PLL1) | BIT(CGA_PLL2),
734753
},
735754
{
736755
.compat = "fsl,p5040-clockgen",
@@ -742,7 +761,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
742761
.cmux_to_group = {
743762
0, 0, 1, 1, -1
744763
},
745-
.pll_mask = 0x0f,
764+
.pll_mask = BIT(PLATFORM_PLL) |
765+
BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3),
746766
},
747767
{
748768
.compat = "fsl,t1023-clockgen",
@@ -757,7 +777,7 @@ static const struct clockgen_chipinfo chipinfo[] = {
757777
.cmux_to_group = {
758778
0, 0, -1
759779
},
760-
.pll_mask = 0x03,
780+
.pll_mask = BIT(PLATFORM_PLL) | BIT(CGA_PLL1),
761781
.flags = CG_PLL_8BIT,
762782
},
763783
{
@@ -770,7 +790,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
770790
.cmux_to_group = {
771791
0, 0, 0, 0, -1
772792
},
773-
.pll_mask = 0x07,
793+
.pll_mask = BIT(PLATFORM_PLL) |
794+
BIT(CGA_PLL1) | BIT(CGA_PLL2),
774795
.flags = CG_PLL_8BIT,
775796
},
776797
{
@@ -786,7 +807,8 @@ static const struct clockgen_chipinfo chipinfo[] = {
786807
.cmux_to_group = {
787808
0, -1
788809
},
789-
.pll_mask = 0x07,
810+
.pll_mask = BIT(PLATFORM_PLL) |
811+
BIT(CGA_PLL1) | BIT(CGA_PLL2),
790812
.flags = CG_PLL_8BIT,
791813
},
792814
{
@@ -802,7 +824,9 @@ static const struct clockgen_chipinfo chipinfo[] = {
802824
.cmux_to_group = {
803825
0, 0, 1, -1
804826
},
805-
.pll_mask = 0x3f,
827+
.pll_mask = BIT(PLATFORM_PLL) |
828+
BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |
829+
BIT(CGB_PLL1) | BIT(CGB_PLL2),
806830
.flags = CG_PLL_8BIT,
807831
},
808832
{},

‎drivers/clk/clk-si570.c

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
*
55
* Copyright (C) 2010, 2011 Ericsson AB.
66
* Copyright (C) 2011 Guenter Roeck.
7-
* Copyright (C) 2011 - 2013 Xilinx Inc.
7+
* Copyright (C) 2011 - 2021 Xilinx Inc.
88
*
99
* Author: Guenter Roeck <[email protected]>
1010
* Sören Brinkmann <[email protected]>
@@ -123,14 +123,18 @@ static int si570_get_divs(struct clk_si570 *data, u64 *rfreq,
123123
* si570_get_defaults() - Get default values
124124
* @data: Driver data structure
125125
* @fout: Factory frequency output
126+
* @skip_recall: If true, don't recall NVM into RAM
126127
* Returns 0 on success, negative errno otherwise.
127128
*/
128-
static int si570_get_defaults(struct clk_si570 *data, u64 fout)
129+
static int si570_get_defaults(struct clk_si570 *data, u64 fout,
130+
bool skip_recall)
129131
{
130132
int err;
131133
u64 fdco;
132134

133-
regmap_write(data->regmap, SI570_REG_CONTROL, SI570_CNTRL_RECALL);
135+
if (!skip_recall)
136+
regmap_write(data->regmap, SI570_REG_CONTROL,
137+
SI570_CNTRL_RECALL);
134138

135139
err = si570_get_divs(data, &data->rfreq, &data->n1, &data->hs_div);
136140
if (err)
@@ -400,6 +404,7 @@ static int si570_probe(struct i2c_client *client,
400404
struct clk_si570 *data;
401405
struct clk_init_data init;
402406
u32 initial_fout, factory_fout, stability;
407+
bool skip_recall;
403408
int err;
404409
enum clk_si570_variant variant = id->driver_data;
405410

@@ -441,14 +446,17 @@ static int si570_probe(struct i2c_client *client,
441446
return err;
442447
}
443448

449+
skip_recall = of_property_read_bool(client->dev.of_node,
450+
"silabs,skip-recall");
451+
444452
data->regmap = devm_regmap_init_i2c(client, &si570_regmap_config);
445453
if (IS_ERR(data->regmap)) {
446454
dev_err(&client->dev, "failed to allocate register map\n");
447455
return PTR_ERR(data->regmap);
448456
}
449457

450458
i2c_set_clientdata(client, data);
451-
err = si570_get_defaults(data, factory_fout);
459+
err = si570_get_defaults(data, factory_fout, skip_recall);
452460
if (err)
453461
return err;
454462

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