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Wenjing Liualexdeucher
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drm/amd/display: update blank state on ODM changes
When we are dynamically adding new ODM slices, we didn't update blank state, if the pipe used by new ODM slice is previously blanked, we will continue outputting blank pixel data on that slice causing right half of the screen showing blank image. The previous fix was a temporary hack to directly update current state when committing new state. This could potentially cause hw and sw state synchronization issues and it is not permitted by dc commit design. Cc: [email protected] Fixes: 7fbf451 ("drm/amd/display: Reinit DPG when exiting dynamic ODM") Reviewed-by: Dillon Varone <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

Lines changed: 9 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1106,29 +1106,6 @@ void dcn20_blank_pixel_data(
11061106
v_active,
11071107
offset);
11081108

1109-
if (!blank && dc->debug.enable_single_display_2to1_odm_policy) {
1110-
/* when exiting dynamic ODM need to reinit DPG state for unused pipes */
1111-
struct pipe_ctx *old_odm_pipe = dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx].next_odm_pipe;
1112-
1113-
odm_pipe = pipe_ctx->next_odm_pipe;
1114-
1115-
while (old_odm_pipe) {
1116-
if (!odm_pipe || old_odm_pipe->pipe_idx != odm_pipe->pipe_idx)
1117-
dc->hwss.set_disp_pattern_generator(dc,
1118-
old_odm_pipe,
1119-
CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
1120-
CONTROLLER_DP_COLOR_SPACE_UDEFINED,
1121-
COLOR_DEPTH_888,
1122-
NULL,
1123-
0,
1124-
0,
1125-
0);
1126-
old_odm_pipe = old_odm_pipe->next_odm_pipe;
1127-
if (odm_pipe)
1128-
odm_pipe = odm_pipe->next_odm_pipe;
1129-
}
1130-
}
1131-
11321109
if (!blank)
11331110
if (stream_res->abm) {
11341111
dc->hwss.set_pipe(pipe_ctx);
@@ -1722,11 +1699,16 @@ static void dcn20_program_pipe(
17221699
struct dc_state *context)
17231700
{
17241701
struct dce_hwseq *hws = dc->hwseq;
1725-
/* Only need to unblank on top pipe */
17261702

1727-
if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
1728-
&& !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
1729-
hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
1703+
/* Only need to unblank on top pipe */
1704+
if (resource_is_pipe_type(pipe_ctx, OTG_MASTER)) {
1705+
if (pipe_ctx->update_flags.bits.enable ||
1706+
pipe_ctx->update_flags.bits.odm ||
1707+
pipe_ctx->stream->update_flags.bits.abm_level)
1708+
hws->funcs.blank_pixel_data(dc, pipe_ctx,
1709+
!pipe_ctx->plane_state ||
1710+
!pipe_ctx->plane_state->visible);
1711+
}
17301712

17311713
/* Only update TG on top pipe */
17321714
if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe

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