Skip to content

Commit 1b02383

Browse files
Marek VasutAlexandre Torgue
authored andcommitted
ARM: dts: stm32: Add ethernet support for DH STM32MP13xx DHCOR DHSBC board
Add ethernet support for the DH STM32MP13xx DHCOR DHSBC carrier board. This carrier board is populated with two gigabit ethernet ports and two Realtek RTL8211F PHYs, both are described in this DT patch. Signed-off-by: Marek Vasut <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
1 parent bf016e1 commit 1b02383

File tree

1 file changed

+56
-0
lines changed

1 file changed

+56
-0
lines changed

arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,8 @@
2222
"st,stm32mp135";
2323

2424
aliases {
25+
ethernet0 = &ethernet1;
26+
ethernet1 = &ethernet2;
2527
serial2 = &usart1;
2628
serial3 = &usart2;
2729
};
@@ -72,6 +74,60 @@
7274
};
7375
};
7476

77+
&ethernet1 {
78+
phy-handle = <&ethphy1>;
79+
phy-mode = "rgmii-id";
80+
pinctrl-0 = <&eth1_rgmii_pins_a>;
81+
pinctrl-1 = <&eth1_rgmii_sleep_pins_a>;
82+
pinctrl-names = "default", "sleep";
83+
st,ext-phyclk;
84+
status = "okay";
85+
86+
mdio {
87+
#address-cells = <1>;
88+
#size-cells = <0>;
89+
compatible = "snps,dwmac-mdio";
90+
91+
ethphy1: ethernet-phy@1 {
92+
/* RTL8211F */
93+
compatible = "ethernet-phy-id001c.c916";
94+
interrupt-parent = <&gpiog>;
95+
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
96+
reg = <1>;
97+
reset-assert-us = <15000>;
98+
reset-deassert-us = <55000>;
99+
reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>;
100+
};
101+
};
102+
};
103+
104+
&ethernet2 {
105+
phy-handle = <&ethphy2>;
106+
phy-mode = "rgmii-id";
107+
pinctrl-0 = <&eth2_rgmii_pins_a>;
108+
pinctrl-1 = <&eth2_rgmii_sleep_pins_a>;
109+
pinctrl-names = "default", "sleep";
110+
st,ext-phyclk;
111+
status = "okay";
112+
113+
mdio {
114+
#address-cells = <1>;
115+
#size-cells = <0>;
116+
compatible = "snps,dwmac-mdio";
117+
118+
ethphy2: ethernet-phy@1 {
119+
/* RTL8211F */
120+
compatible = "ethernet-phy-id001c.c916";
121+
interrupt-parent = <&gpiog>;
122+
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
123+
reg = <1>;
124+
reset-assert-us = <15000>;
125+
reset-deassert-us = <55000>;
126+
reset-gpios = <&gpiog 8 GPIO_ACTIVE_LOW>;
127+
};
128+
};
129+
};
130+
75131
&gpioa {
76132
gpio-line-names = "", "", "", "",
77133
"", "DHSBC_USB_PWR_CC1", "", "",

0 commit comments

Comments
 (0)