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Merge branches 'clk-devm', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into clk-next
* clk-devm: clk: provide devm_clk_get_optional_enabled_with_rate() clk: fixed-rate: add devm_clk_hw_register_fixed_rate_parent_data() * clk-samsung: clk: samsung: add top clock support for ExynosAuto v920 SoC clk: samsung: clk-pll: Add support for pll_531x dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings clk: samsung: exynos7885: Add USB related clocks to CMU_FSYS clk: samsung: clk-pll: Add support for pll_1418x clk: samsung: exynosautov9: add dpum clock support dt-bindings: clock: exynosautov9: add dpum clock clk: samsung: exynos7885: Add missing MUX clocks from PLLs in CMU_TOP clk: samsung: exynos7885: Update CLKS_NR_FSYS after bindings fix dt-bindings: clock: exynos7885: Add indices for USB clocks dt-bindings: clock: exynos7885: Add CMU_TOP PLL MUX indices dt-bindings: clock: exynos7885: Fix duplicated binding clk: samsung: exynos850: Add TMU clock dt-bindings: clock: exynos850: Add TMU clock * clk-rockchip: dt-bindings: clock, reset: fix top-comment indentation rk3576 headers clk: rockchip: remove unused mclk_pdm0_p/pdm0_p definitions clk: rockchip: fix error for unknown clocks clk: rockchip: rk3588: drop unused code clk: rockchip: Add clock controller for the RK3576 clk: rockchip: Add new pll type pll_rk3588_ddr dt-bindings: clock, reset: Add support for rk3576 dt-bindings: clock: rockchip,rk3588-cru: drop unneeded assigned-clocks clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_p dt-bindings: clock: rockchip: remove CLK_NR_CLKS and CLKPMU_NR_CLKS clk: rockchip: rk3399: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage clk: rockchip: rk3368: Drop CLK_NR_CLKS usage clk: rockchip: rk3328: Drop CLK_NR_CLKS usage clk: rockchip: rk3308: Drop CLK_NR_CLKS usage clk: rockchip: rk3288: Drop CLK_NR_CLKS usage clk: rockchip: rk3228: Drop CLK_NR_CLKS usage clk: rockchip: rk3036: Drop CLK_NR_CLKS usage clk: rockchip: px30: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228 * clk-qcom: (47 commits) clk: qcom: videocc-sm8550: Use HW_CTRL_TRIGGER flag for video GDSC's clk: qcom: dispcc-sm8250: use special function for Lucid 5LPE PLL clk: qcom: dispcc-sm8250: use CLK_SET_RATE_PARENT for branch clocks clk: qcom: ipq5332: Use icc-clk for enabling NoC related clocks clk: qcom: ipq5332: Register gcc_qdss_tsctr_clk_src dt-bindings: usb: qcom,dwc3: Update ipq5332 clock details dt-bindings: interconnect: Add Qualcomm IPQ5332 support clk: qcom: gcc-msm8998: Add Q6 BIMC and LPASS core, ADSP SMMU clocks dt-bindings: clock: gcc-msm8998: Add Q6 and LPASS clocks definitions clk: qcom: Fix SM_CAMCC_8150 dependencies clk: qcom: gcc-sm8150: De-register gcc_cpuss_ahb_clk_src clk: qcom: gcc-sc8180x: Fix the sdcc2 and sdcc4 clocks freq table clk: qcom: gcc-sc8180x: Add GPLL9 support dt-bindings: clock: qcom: Add GPLL9 support on gcc-sc8180x clk: qcom: gcc-sc8180x: Register QUPv3 RCGs for DFS on sc8180x clk: qcom: clk-rpmh: Fix overflow in BCM vote dt-bindings: clock: qcom: Drop required-opps in required on SM8650 camcc dt-bindings: clock: qcom: Drop required-opps in required on sm8650 videocc dt-bindings: clock: qcom,qcs404-turingcc: convert to dtschema dt-bindings: clock: Add x1e80100 LPASSCC reset controller ...
5 parents 6629108 + 9934a1b + 4e52054 + eb3b3f5 + 82cf3b8 commit 1b189f7

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lines changed

‎Documentation/devicetree/bindings/clock/qcom,a53pll.yaml

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@@ -21,6 +21,7 @@ properties:
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- qcom,ipq6018-a53pll
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- qcom,ipq8074-a53pll
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- qcom,ipq9574-a73pll
24+
- qcom,msm8226-a7pll
2425
- qcom,msm8916-a53pll
2526
- qcom,msm8939-a53pll
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@@ -40,6 +41,9 @@ properties:
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operating-points-v2: true
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opp-table:
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type: object
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required:
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- compatible
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- reg

‎Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml

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@@ -31,6 +31,8 @@ properties:
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- description: USB PCIE wrapper pipe clock source
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'#power-domain-cells': false
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'#interconnect-cells':
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const: 1
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required:
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- compatible

‎Documentation/devicetree/bindings/clock/qcom,qcs404-turingcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,qcs404-turingcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Turing Clock & Reset Controller on QCS404
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maintainers:
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- Bjorn Andersson <[email protected]>
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properties:
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compatible:
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const: qcom,qcs404-turingcc
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
36+
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-qcs404.h>
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clock-controller@800000 {
41+
compatible = "qcom,qcs404-turingcc";
42+
reg = <0x00800000 0x30000>;
43+
clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};

‎Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml

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@@ -18,9 +18,16 @@ description: |
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properties:
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compatible:
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enum:
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- qcom,sc8280xp-lpassaudiocc
23-
- qcom,sc8280xp-lpasscc
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oneOf:
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- enum:
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- qcom,sc8280xp-lpassaudiocc
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- qcom,sc8280xp-lpasscc
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- items:
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- const: qcom,x1e80100-lpassaudiocc
27+
- const: qcom,sc8280xp-lpassaudiocc
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- items:
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- const: qcom,x1e80100-lpasscc
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- const: qcom,sc8280xp-lpasscc
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reg:
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maxItems: 1

‎Documentation/devicetree/bindings/clock/qcom,sm4450-camcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm4450-camcc.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Qualcomm Camera Clock & Reset Controller on SM4450
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9+
maintainers:
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- Ajit Pandey <[email protected]>
11+
- Taniya Das <[email protected]>
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13+
description: |
14+
Qualcomm camera clock control module provides the clocks, resets and power
15+
domains on SM4450
16+
17+
See also:: include/dt-bindings/clock/qcom,sm4450-camcc.h
18+
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properties:
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compatible:
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const: qcom,sm4450-camcc
22+
23+
reg:
24+
maxItems: 1
25+
26+
clocks:
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items:
28+
- description: Board XO source
29+
- description: Camera AHB clock source from GCC
30+
31+
'#clock-cells':
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const: 1
33+
34+
'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
52+
#include <dt-bindings/clock/qcom,rpmh.h>
53+
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
54+
clock-controller@ade0000 {
55+
compatible = "qcom,sm4450-camcc";
56+
reg = <0x0ade0000 0x20000>;
57+
clocks = <&rpmhcc RPMH_CXO_CLK>,
58+
<&gcc GCC_CAMERA_AHB_CLK>;
59+
#clock-cells = <1>;
60+
#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,sm4450-dispcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
4+
$id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Qualcomm Display Clock & Reset Controller on SM4450
8+
9+
maintainers:
10+
- Ajit Pandey <[email protected]>
11+
- Taniya Das <[email protected]>
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13+
description: |
14+
Qualcomm display clock control module provides the clocks, resets and power
15+
domains on SM4450
16+
17+
See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h
18+
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properties:
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compatible:
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const: qcom,sm4450-dispcc
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Board XO source
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- description: Board active XO source
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- description: Display AHB clock source from GCC
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- description: sleep clock source
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY0
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
56+
#include <dt-bindings/clock/qcom,rpmh.h>
57+
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
58+
clock-controller@af00000 {
59+
compatible = "qcom,sm4450-dispcc";
60+
reg = <0x0af00000 0x20000>;
61+
clocks = <&rpmhcc RPMH_CXO_CLK>,
62+
<&rpmhcc RPMH_CXO_CLK_A>,
63+
<&gcc GCC_DISP_AHB_CLK>,
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<&sleep_clk>,
65+
<&dsi0_phy_pll_out_byteclk>,
66+
<&dsi0_phy_pll_out_dsiclk>;
67+
#clock-cells = <1>;
68+
#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,sm8150-camcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm8150-camcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Qualcomm Camera Clock & Reset Controller on SM8150
8+
9+
maintainers:
10+
- Satya Priya Kakitapalli <[email protected]>
11+
12+
description: |
13+
Qualcomm camera clock control module provides the clocks, resets and
14+
power domains on SM8150.
15+
16+
See also:: include/dt-bindings/clock/qcom,sm8150-camcc.h
17+
18+
properties:
19+
compatible:
20+
const: qcom,sm8150-camcc
21+
22+
reg:
23+
maxItems: 1
24+
25+
clocks:
26+
items:
27+
- description: Board XO source
28+
- description: Camera AHB clock from GCC
29+
30+
power-domains:
31+
maxItems: 1
32+
description:
33+
A phandle and PM domain specifier for the MMCX power domain.
34+
35+
required-opps:
36+
maxItems: 1
37+
description:
38+
A phandle to an OPP node describing required MMCX performance point.
39+
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'#clock-cells':
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const: 1
42+
43+
'#reset-cells':
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const: 1
45+
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'#power-domain-cells':
47+
const: 1
48+
49+
required:
50+
- compatible
51+
- reg
52+
- clocks
53+
- power-domains
54+
- required-opps
55+
- '#clock-cells'
56+
- '#reset-cells'
57+
- '#power-domain-cells'
58+
59+
additionalProperties: false
60+
61+
examples:
62+
- |
63+
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
64+
#include <dt-bindings/clock/qcom,rpmh.h>
65+
#include <dt-bindings/power/qcom-rpmpd.h>
66+
clock-controller@ad00000 {
67+
compatible = "qcom,sm8150-camcc";
68+
reg = <0x0ad00000 0x10000>;
69+
clocks = <&rpmhcc RPMH_CXO_CLK>,
70+
<&gcc GCC_CAMERA_AHB_CLK>;
71+
power-domains = <&rpmhpd SM8150_MMCX>;
72+
required-opps = <&rpmhpd_opp_low_svs>;
73+
#clock-cells = <1>;
74+
#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml

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include/dt-bindings/clock/qcom,sm8650-camcc.h
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include/dt-bindings/clock/qcom,x1e80100-camcc.h
2323
24-
allOf:
25-
- $ref: qcom,gcc.yaml#
26-
2724
properties:
2825
compatible:
2926
enum:
@@ -57,7 +54,21 @@ required:
5754
- compatible
5855
- clocks
5956
- power-domains
60-
- required-opps
57+
58+
allOf:
59+
- $ref: qcom,gcc.yaml#
60+
- if:
61+
properties:
62+
compatible:
63+
contains:
64+
enum:
65+
- qcom,sc8280xp-camcc
66+
- qcom,sm8450-camcc
67+
- qcom,sm8550-camcc
68+
- qcom,x1e80100-camcc
69+
then:
70+
required:
71+
- required-opps
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unevaluatedProperties: false
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‎Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml

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@@ -14,6 +14,7 @@ description: |
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domains on Qualcomm SoCs.
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See also::
17+
include/dt-bindings/clock/qcom,sm4450-gpucc.h
1718
include/dt-bindings/clock/qcom,sm8450-gpucc.h
1819
include/dt-bindings/clock/qcom,sm8550-gpucc.h
1920
include/dt-bindings/reset/qcom,sm8450-gpucc.h
@@ -23,6 +24,7 @@ description: |
2324
properties:
2425
compatible:
2526
enum:
27+
- qcom,sm4450-gpucc
2628
- qcom,sm8450-gpucc
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- qcom,sm8550-gpucc
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- qcom,sm8650-gpucc

‎Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml

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- compatible
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- clocks
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- power-domains
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- required-opps
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- '#power-domain-cells'
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5049
allOf:
5150
- $ref: qcom,gcc.yaml#
51+
- if:
52+
properties:
53+
compatible:
54+
contains:
55+
enum:
56+
- qcom,sm8450-videocc
57+
- qcom,sm8550-videocc
58+
then:
59+
required:
60+
- required-opps
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unevaluatedProperties: false
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