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airliedairlied
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Merge tag 'amd-drm-fixes-6.12-2024-11-14' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-6.12-2024-11-14: amdgpu: - PSR fix - Panel replay fixes - DML fix - vblank power fix - Fix video caps - SMU 14.0 fix - GPUVM fix - MES 12 fix - APU carve out fix - DC vbios fix - NBIO fix Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents 99d051c + 7013a82 commit 1eb0de8

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17 files changed

+117
-96
lines changed

17 files changed

+117
-96
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,8 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
161161
* When GTT is just an alternative to VRAM make sure that we
162162
* only use it as fallback and still try to fill up VRAM first.
163163
*/
164-
if (domain & abo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM)
164+
if (domain & abo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&
165+
!(adev->flags & AMD_IS_APU))
165166
places[c].flags |= TTM_PL_FLAG_FALLBACK;
166167
c++;
167168
}

‎drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1124,15 +1124,19 @@ static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev,
11241124
uint64_t *flags)
11251125
{
11261126
struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1127-
bool is_vram = bo->tbo.resource->mem_type == TTM_PL_VRAM;
1128-
bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT | AMDGPU_GEM_CREATE_EXT_COHERENT);
1127+
bool is_vram = bo->tbo.resource &&
1128+
bo->tbo.resource->mem_type == TTM_PL_VRAM;
1129+
bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
1130+
AMDGPU_GEM_CREATE_EXT_COHERENT);
11291131
bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT;
11301132
bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED;
11311133
struct amdgpu_vm *vm = mapping->bo_va->base.vm;
11321134
unsigned int mtype_local, mtype;
11331135
bool snoop = false;
11341136
bool is_local;
11351137

1138+
dma_resv_assert_held(bo->tbo.base.resv);
1139+
11361140
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
11371141
case IP_VERSION(9, 4, 1):
11381142
case IP_VERSION(9, 4, 2):
@@ -1251,9 +1255,8 @@ static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
12511255
*flags &= ~AMDGPU_PTE_VALID;
12521256
}
12531257

1254-
if (bo && bo->tbo.resource)
1255-
gmc_v9_0_get_coherence_flags(adev, mapping->bo_va->base.bo,
1256-
mapping, flags);
1258+
if ((*flags & AMDGPU_PTE_VALID) && bo)
1259+
gmc_v9_0_get_coherence_flags(adev, bo, mapping, flags);
12571260
}
12581261

12591262
static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev,

‎drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -550,7 +550,7 @@ static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe)
550550
mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER;
551551
mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;
552552
mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
553-
mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100;
553+
mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 0xa;
554554

555555
return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
556556
&mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt),

‎drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -247,6 +247,12 @@ static void nbio_v7_7_init_registers(struct amdgpu_device *adev)
247247
if (def != data)
248248
WREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3, data);
249249

250+
switch (adev->ip_versions[NBIO_HWIP][0]) {
251+
case IP_VERSION(7, 7, 0):
252+
data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) & ~BIT(23);
253+
WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4, data);
254+
break;
255+
}
250256
}
251257

252258
static void nbio_v7_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,

‎drivers/gpu/drm/amd/amdgpu/nv.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -67,8 +67,8 @@ static const struct amd_ip_funcs nv_common_ip_funcs;
6767

6868
/* Navi */
6969
static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = {
70-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
71-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
70+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
71+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 0)},
7272
};
7373

7474
static const struct amdgpu_video_codecs nv_video_codecs_encode = {
@@ -94,8 +94,8 @@ static const struct amdgpu_video_codecs nv_video_codecs_decode = {
9494

9595
/* Sienna Cichlid */
9696
static const struct amdgpu_video_codec_info sc_video_codecs_encode_array[] = {
97-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},
98-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},
97+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
98+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
9999
};
100100

101101
static const struct amdgpu_video_codecs sc_video_codecs_encode = {
@@ -136,8 +136,8 @@ static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 = {
136136

137137
/* SRIOV Sienna Cichlid, not const since data is controlled by host */
138138
static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = {
139-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},
140-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},
139+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
140+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
141141
};
142142

143143
static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] = {

‎drivers/gpu/drm/amd/amdgpu/soc15.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -90,8 +90,8 @@ static const struct amd_ip_funcs soc15_common_ip_funcs;
9090
/* Vega, Raven, Arcturus */
9191
static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =
9292
{
93-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
94-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
93+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
94+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 0)},
9595
};
9696

9797
static const struct amdgpu_video_codecs vega_video_codecs_encode =

‎drivers/gpu/drm/amd/amdgpu/soc21.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -49,13 +49,13 @@ static const struct amd_ip_funcs soc21_common_ip_funcs;
4949

5050
/* SOC21 */
5151
static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
52-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
52+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
5353
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
5454
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
5555
};
5656

5757
static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
58-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
58+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
5959
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
6060
};
6161

@@ -96,14 +96,14 @@ static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = {
9696

9797
/* SRIOV SOC21, not const since data is controlled by host */
9898
static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
99-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
100-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
99+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
100+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
101101
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
102102
};
103103

104104
static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
105-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
106-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
105+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
106+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
107107
};
108108

109109
static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = {

‎drivers/gpu/drm/amd/amdgpu/soc24.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@
4848
static const struct amd_ip_funcs soc24_common_ip_funcs;
4949

5050
static const struct amdgpu_video_codec_info vcn_5_0_0_video_codecs_encode_array_vcn0[] = {
51-
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
51+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
5252
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
5353
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
5454
};

‎drivers/gpu/drm/amd/amdgpu/vi.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -136,15 +136,15 @@ static const struct amdgpu_video_codec_info polaris_video_codecs_encode_array[]
136136
{
137137
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
138138
.max_width = 4096,
139-
.max_height = 2304,
140-
.max_pixels_per_frame = 4096 * 2304,
139+
.max_height = 4096,
140+
.max_pixels_per_frame = 4096 * 4096,
141141
.max_level = 0,
142142
},
143143
{
144144
.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
145145
.max_width = 4096,
146-
.max_height = 2304,
147-
.max_pixels_per_frame = 4096 * 2304,
146+
.max_height = 4096,
147+
.max_pixels_per_frame = 4096 * 4096,
148148
.max_level = 0,
149149
},
150150
};

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

Lines changed: 60 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -6762,7 +6762,7 @@ create_stream_for_sink(struct drm_connector *connector,
67626762
if (stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22)
67636763
tf = TRANSFER_FUNC_GAMMA_22;
67646764
mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6765-
aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6765+
aconnector->sr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
67666766

67676767
}
67686768
finish:
@@ -8875,6 +8875,56 @@ static void amdgpu_dm_update_cursor(struct drm_plane *plane,
88758875
}
88768876
}
88778877

8878+
static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach,
8879+
const struct dm_crtc_state *acrtc_state,
8880+
const u64 current_ts)
8881+
{
8882+
struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;
8883+
struct replay_settings *pr = &acrtc_state->stream->link->replay_settings;
8884+
struct amdgpu_dm_connector *aconn =
8885+
(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8886+
8887+
if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
8888+
if (pr->config.replay_supported && !pr->replay_feature_enabled)
8889+
amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn);
8890+
else if (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8891+
!psr->psr_feature_enabled)
8892+
if (!aconn->disallow_edp_enter_psr)
8893+
amdgpu_dm_link_setup_psr(acrtc_state->stream);
8894+
}
8895+
8896+
/* Decrement skip count when SR is enabled and we're doing fast updates. */
8897+
if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8898+
(psr->psr_feature_enabled || pr->config.replay_supported)) {
8899+
if (aconn->sr_skip_count > 0)
8900+
aconn->sr_skip_count--;
8901+
8902+
/* Allow SR when skip count is 0. */
8903+
acrtc_attach->dm_irq_params.allow_sr_entry = !aconn->sr_skip_count;
8904+
8905+
/*
8906+
* If sink supports PSR SU/Panel Replay, there is no need to rely on
8907+
* a vblank event disable request to enable PSR/RP. PSR SU/RP
8908+
* can be enabled immediately once OS demonstrates an
8909+
* adequate number of fast atomic commits to notify KMD
8910+
* of update events. See `vblank_control_worker()`.
8911+
*/
8912+
if (acrtc_attach->dm_irq_params.allow_sr_entry &&
8913+
#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8914+
!amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8915+
#endif
8916+
(current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) {
8917+
if (pr->replay_feature_enabled && !pr->replay_allow_active)
8918+
amdgpu_dm_replay_enable(acrtc_state->stream, true);
8919+
if (psr->psr_version >= DC_PSR_VERSION_SU_1 &&
8920+
!psr->psr_allow_active && !aconn->disallow_edp_enter_psr)
8921+
amdgpu_dm_psr_enable(acrtc_state->stream);
8922+
}
8923+
} else {
8924+
acrtc_attach->dm_irq_params.allow_sr_entry = false;
8925+
}
8926+
}
8927+
88788928
static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
88798929
struct drm_device *dev,
88808930
struct amdgpu_display_manager *dm,
@@ -9028,7 +9078,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
90289078
* during the PSR-SU was disabled.
90299079
*/
90309080
if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
9031-
acrtc_attach->dm_irq_params.allow_psr_entry &&
9081+
acrtc_attach->dm_irq_params.allow_sr_entry &&
90329082
#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
90339083
!amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
90349084
#endif
@@ -9203,9 +9253,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
92039253
bundle->stream_update.abm_level = &acrtc_state->abm_level;
92049254

92059255
mutex_lock(&dm->dc_lock);
9206-
if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
9207-
acrtc_state->stream->link->psr_settings.psr_allow_active)
9208-
amdgpu_dm_psr_disable(acrtc_state->stream);
9256+
if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
9257+
if (acrtc_state->stream->link->replay_settings.replay_allow_active)
9258+
amdgpu_dm_replay_disable(acrtc_state->stream);
9259+
if (acrtc_state->stream->link->psr_settings.psr_allow_active)
9260+
amdgpu_dm_psr_disable(acrtc_state->stream);
9261+
}
92099262
mutex_unlock(&dm->dc_lock);
92109263

92119264
/*
@@ -9246,57 +9299,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
92469299
dm_update_pflip_irq_state(drm_to_adev(dev),
92479300
acrtc_attach);
92489301

9249-
if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
9250-
if (acrtc_state->stream->link->replay_settings.config.replay_supported &&
9251-
!acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
9252-
struct amdgpu_dm_connector *aconn =
9253-
(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
9254-
amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn);
9255-
} else if (acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
9256-
!acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
9257-
9258-
struct amdgpu_dm_connector *aconn = (struct amdgpu_dm_connector *)
9259-
acrtc_state->stream->dm_stream_context;
9260-
9261-
if (!aconn->disallow_edp_enter_psr)
9262-
amdgpu_dm_link_setup_psr(acrtc_state->stream);
9263-
}
9264-
}
9265-
9266-
/* Decrement skip count when PSR is enabled and we're doing fast updates. */
9267-
if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
9268-
acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
9269-
struct amdgpu_dm_connector *aconn =
9270-
(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
9271-
9272-
if (aconn->psr_skip_count > 0)
9273-
aconn->psr_skip_count--;
9274-
9275-
/* Allow PSR when skip count is 0. */
9276-
acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
9277-
9278-
/*
9279-
* If sink supports PSR SU, there is no need to rely on
9280-
* a vblank event disable request to enable PSR. PSR SU
9281-
* can be enabled immediately once OS demonstrates an
9282-
* adequate number of fast atomic commits to notify KMD
9283-
* of update events. See `vblank_control_worker()`.
9284-
*/
9285-
if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
9286-
acrtc_attach->dm_irq_params.allow_psr_entry &&
9287-
#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
9288-
!amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
9289-
#endif
9290-
!acrtc_state->stream->link->psr_settings.psr_allow_active &&
9291-
!aconn->disallow_edp_enter_psr &&
9292-
(timestamp_ns -
9293-
acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
9294-
500000000)
9295-
amdgpu_dm_psr_enable(acrtc_state->stream);
9296-
} else {
9297-
acrtc_attach->dm_irq_params.allow_psr_entry = false;
9298-
}
9299-
9302+
amdgpu_dm_enable_self_refresh(acrtc_attach, acrtc_state, timestamp_ns);
93009303
mutex_unlock(&dm->dc_lock);
93019304
}
93029305

@@ -12080,7 +12083,7 @@ static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
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break;
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}
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12083-
while (j < EDID_LENGTH) {
12086+
while (j < EDID_LENGTH - sizeof(struct amd_vsdb_block)) {
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struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j];
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unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);
1208612089

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