|
1151 | 1151 | };
|
1152 | 1152 | };
|
1153 | 1153 |
|
| 1154 | + icssg0_iep0: iep@2e000 { |
| 1155 | + compatible = "ti,am654-icss-iep"; |
| 1156 | + reg = <0x2e000 0x1000>; |
| 1157 | + clocks = <&icssg0_iepclk_mux>; |
| 1158 | + }; |
| 1159 | + |
| 1160 | + icssg0_iep1: iep@2f000 { |
| 1161 | + compatible = "ti,am654-icss-iep"; |
| 1162 | + reg = <0x2f000 0x1000>; |
| 1163 | + clocks = <&icssg0_iepclk_mux>; |
| 1164 | + }; |
| 1165 | + |
1154 | 1166 | icssg0_mii_rt: mii-rt@32000 {
|
1155 | 1167 | compatible = "ti,pruss-mii", "syscon";
|
1156 | 1168 | reg = <0x32000 0x100>;
|
|
1293 | 1305 | };
|
1294 | 1306 | };
|
1295 | 1307 |
|
| 1308 | + icssg1_iep0: iep@2e000 { |
| 1309 | + compatible = "ti,am654-icss-iep"; |
| 1310 | + reg = <0x2e000 0x1000>; |
| 1311 | + clocks = <&icssg1_iepclk_mux>; |
| 1312 | + }; |
| 1313 | + |
| 1314 | + icssg1_iep1: iep@2f000 { |
| 1315 | + compatible = "ti,am654-icss-iep"; |
| 1316 | + reg = <0x2f000 0x1000>; |
| 1317 | + clocks = <&icssg1_iepclk_mux>; |
| 1318 | + }; |
| 1319 | + |
1296 | 1320 | icssg1_mii_rt: mii-rt@32000 {
|
1297 | 1321 | compatible = "ti,pruss-mii", "syscon";
|
1298 | 1322 | reg = <0x32000 0x100>;
|
|
1435 | 1459 | };
|
1436 | 1460 | };
|
1437 | 1461 |
|
| 1462 | + icssg2_iep0: iep@2e000 { |
| 1463 | + compatible = "ti,am654-icss-iep"; |
| 1464 | + reg = <0x2e000 0x1000>; |
| 1465 | + clocks = <&icssg2_iepclk_mux>; |
| 1466 | + }; |
| 1467 | + |
| 1468 | + icssg2_iep1: iep@2f000 { |
| 1469 | + compatible = "ti,am654-icss-iep"; |
| 1470 | + reg = <0x2f000 0x1000>; |
| 1471 | + clocks = <&icssg2_iepclk_mux>; |
| 1472 | + }; |
| 1473 | + |
1438 | 1474 | icssg2_mii_rt: mii-rt@32000 {
|
1439 | 1475 | compatible = "ti,pruss-mii", "syscon";
|
1440 | 1476 | reg = <0x32000 0x100>;
|
|
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