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Merge branch 'remotes/lorenzo/pci/rcar'
- Clear bit 0 of MACCTLR before PCIETCTLR.CFINIT per manual (Yoshihiro Shimoda) - Remove unnecessary header include from rcar (Andrew Murray) - Tighten register index checking for rcar inbound range programming (Marek Vasut) - Fix rcar inbound range alignment calculation to improve packing of multiple entries (Marek Vasut) - Update rcar MACCTLR setting to match documentation (Yoshihiro Shimoda) * remotes/lorenzo/pci/rcar: PCI: rcar: Fix missing MACCTLR register setting in initialization sequence PCI: rcar: Recalculate inbound range alignment for each controller entry PCI: rcar: Move the inbound index check PCI: rcar: Remove unnecessary header include (../pci.h)
2 parents 4940330 + 7c7e53e commit 21cea0c

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-23
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+27
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drivers/pci/controller/pcie-rcar.c

Lines changed: 27 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -30,8 +30,6 @@
3030
#include <linux/pm_runtime.h>
3131
#include <linux/slab.h>
3232

33-
#include "../pci.h"
34-
3533
#define PCIECAR 0x000010
3634
#define PCIECCTLR 0x000018
3735
#define CONFIG_SEND_ENABLE BIT(31)
@@ -93,8 +91,11 @@
9391
#define LINK_SPEED_2_5GTS (1 << 16)
9492
#define LINK_SPEED_5_0GTS (2 << 16)
9593
#define MACCTLR 0x011058
94+
#define MACCTLR_NFTS_MASK GENMASK(23, 16) /* The name is from SH7786 */
9695
#define SPEED_CHANGE BIT(24)
9796
#define SCRAMBLE_DISABLE BIT(27)
97+
#define LTSMDIS BIT(31)
98+
#define MACCTLR_INIT_VAL (LTSMDIS | MACCTLR_NFTS_MASK)
9899
#define PMSR 0x01105c
99100
#define MACS2R 0x011078
100101
#define MACCGSPSETR 0x011084
@@ -615,6 +616,8 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
615616
if (IS_ENABLED(CONFIG_PCI_MSI))
616617
rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
617618

619+
rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
620+
618621
/* Finish initialization - establish a PCI Express link */
619622
rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
620623

@@ -1029,25 +1032,30 @@ static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
10291032
if (restype & IORESOURCE_PREFETCH)
10301033
flags |= LAM_PREFETCH;
10311034

1032-
/*
1033-
* If the size of the range is larger than the alignment of the start
1034-
* address, we have to use multiple entries to perform the mapping.
1035-
*/
1036-
if (cpu_addr > 0) {
1037-
unsigned long nr_zeros = __ffs64(cpu_addr);
1038-
u64 alignment = 1ULL << nr_zeros;
1035+
while (cpu_addr < cpu_end) {
1036+
if (idx >= MAX_NR_INBOUND_MAPS - 1) {
1037+
dev_err(pcie->dev, "Failed to map inbound regions!\n");
1038+
return -EINVAL;
1039+
}
1040+
/*
1041+
* If the size of the range is larger than the alignment of
1042+
* the start address, we have to use multiple entries to
1043+
* perform the mapping.
1044+
*/
1045+
if (cpu_addr > 0) {
1046+
unsigned long nr_zeros = __ffs64(cpu_addr);
1047+
u64 alignment = 1ULL << nr_zeros;
10391048

1040-
size = min(range->size, alignment);
1041-
} else {
1042-
size = range->size;
1043-
}
1044-
/* Hardware supports max 4GiB inbound region */
1045-
size = min(size, 1ULL << 32);
1049+
size = min(range->size, alignment);
1050+
} else {
1051+
size = range->size;
1052+
}
1053+
/* Hardware supports max 4GiB inbound region */
1054+
size = min(size, 1ULL << 32);
10461055

1047-
mask = roundup_pow_of_two(size) - 1;
1048-
mask &= ~0xf;
1056+
mask = roundup_pow_of_two(size) - 1;
1057+
mask &= ~0xf;
10491058

1050-
while (cpu_addr < cpu_end) {
10511059
/*
10521060
* Set up 64-bit inbound regions as the range parser doesn't
10531061
* distinguish between 32 and 64-bit types.
@@ -1067,11 +1075,6 @@ static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
10671075
pci_addr += size;
10681076
cpu_addr += size;
10691077
idx += 2;
1070-
1071-
if (idx > MAX_NR_INBOUND_MAPS) {
1072-
dev_err(pcie->dev, "Failed to map inbound regions!\n");
1073-
return -EINVAL;
1074-
}
10751078
}
10761079
*index = idx;
10771080

@@ -1237,6 +1240,7 @@ static int rcar_pcie_resume_noirq(struct device *dev)
12371240
return 0;
12381241

12391242
/* Re-establish the PCIe link */
1243+
rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
12401244
rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
12411245
return rcar_pcie_wait_for_dl(pcie);
12421246
}

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