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bjorn-helgaasbjorn-helgaas
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Merge branch 'remotes/lorenzo/pci/dwc'
- Add qcom ipq806x support (Ansuel Smith) - Support max-link-speed DT property for qcom (Sham Muthayyan) - Use PCI core #defines instead of adding qcom-specific ones (Ansuel Smith) - Convert to devm_platform_ioremap_resource_byname() instead of open-coding platform_get_resource_byname() and devm_ioremap_resource() for dra7xx, keystone, artpec6, designware-plat, histb, intel-gw, kirin, qcom, uniphier (Dejin Zheng) - Remove non-ECAM HiSilicon hip05/hip06 driver (Rob Herring) * remotes/lorenzo/pci/dwc: PCI: dwc: hisi: Remove non-ECAM HiSilicon hip05/hip06 driver PCI: dwc: Convert to devm_platform_ioremap_resource_byname() PCI: qcom: Replace define with standard value PCI: qcom: Support pci speed set for ipq806x dt-bindings: PCI: qcom: Add ipq8064 rev 2 variant PCI: qcom: Add ipq8064 rev2 variant PCI: qcom: Add support for tx term offset for rev 2.1.0 PCI: qcom: Define some PARF params needed for ipq8064 SoC PCI: qcom: Use bulk clk api and assert on error dt-bindings: PCI: qcom: Add ext reset PCI: qcom: Add missing reset for ipq806x PCI: qcom: Change duplicate PCI reset to phy reset dt-bindings: PCI: qcom: Add missing clks PCI: qcom: Add missing ipq806x clocks in PCIe driver
2 parents 13a7733 + c2fa6cf commit 2641802

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11 files changed

+151
-338
lines changed

11 files changed

+151
-338
lines changed

‎Documentation/devicetree/bindings/pci/qcom,pcie.txt

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@
55
Value type: <stringlist>
66
Definition: Value should contain
77
- "qcom,pcie-ipq8064" for ipq8064
8+
- "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
89
- "qcom,pcie-apq8064" for apq8064
910
- "qcom,pcie-apq8084" for apq8084
1011
- "qcom,pcie-msm8996" for msm8996 or apq8096
@@ -90,6 +91,8 @@
9091
Definition: Should contain the following entries
9192
- "core" Clocks the pcie hw block
9293
- "phy" Clocks the pcie PHY block
94+
- "aux" Clocks the pcie AUX block
95+
- "ref" Clocks the pcie ref block
9396
- clock-names:
9497
Usage: required for apq8084/ipq4019
9598
Value type: <stringlist>
@@ -177,6 +180,7 @@
177180
- "pwr" PWR reset
178181
- "ahb" AHB reset
179182
- "phy_ahb" PHY AHB reset
183+
- "ext" EXT reset
180184

181185
- reset-names:
182186
Usage: required for ipq8074
@@ -277,14 +281,17 @@
277281
<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
278282
clocks = <&gcc PCIE_A_CLK>,
279283
<&gcc PCIE_H_CLK>,
280-
<&gcc PCIE_PHY_CLK>;
281-
clock-names = "core", "iface", "phy";
284+
<&gcc PCIE_PHY_CLK>,
285+
<&gcc PCIE_AUX_CLK>,
286+
<&gcc PCIE_ALT_REF_CLK>;
287+
clock-names = "core", "iface", "phy", "aux", "ref";
282288
resets = <&gcc PCIE_ACLK_RESET>,
283289
<&gcc PCIE_HCLK_RESET>,
284290
<&gcc PCIE_POR_RESET>,
285291
<&gcc PCIE_PCI_RESET>,
286-
<&gcc PCIE_PHY_RESET>;
287-
reset-names = "axi", "ahb", "por", "pci", "phy";
292+
<&gcc PCIE_PHY_RESET>,
293+
<&gcc PCIE_EXT_RESET>;
294+
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
288295
pinctrl-0 = <&pcie_pins_default>;
289296
pinctrl-names = "default";
290297
};

‎drivers/pci/controller/dwc/pci-dra7xx.c

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -593,13 +593,12 @@ static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
593593
ep = &pci->ep;
594594
ep->ops = &pcie_ep_ops;
595595

596-
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics");
597-
pci->dbi_base = devm_ioremap_resource(dev, res);
596+
pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "ep_dbics");
598597
if (IS_ERR(pci->dbi_base))
599598
return PTR_ERR(pci->dbi_base);
600599

601-
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics2");
602-
pci->dbi_base2 = devm_ioremap_resource(dev, res);
600+
pci->dbi_base2 =
601+
devm_platform_ioremap_resource_byname(pdev, "ep_dbics2");
603602
if (IS_ERR(pci->dbi_base2))
604603
return PTR_ERR(pci->dbi_base2);
605604

@@ -626,7 +625,6 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
626625
struct dw_pcie *pci = dra7xx->pci;
627626
struct pcie_port *pp = &pci->pp;
628627
struct device *dev = pci->dev;
629-
struct resource *res;
630628

631629
pp->irq = platform_get_irq(pdev, 1);
632630
if (pp->irq < 0) {
@@ -638,8 +636,7 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
638636
if (ret < 0)
639637
return ret;
640638

641-
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
642-
pci->dbi_base = devm_ioremap_resource(dev, res);
639+
pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "rc_dbics");
643640
if (IS_ERR(pci->dbi_base))
644641
return PTR_ERR(pci->dbi_base);
645642

‎drivers/pci/controller/dwc/pci-keystone.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1323,8 +1323,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
13231323
}
13241324

13251325
if (pci->version >= 0x480A) {
1326-
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu");
1327-
atu_base = devm_ioremap_resource(dev, res);
1326+
atu_base = devm_platform_ioremap_resource_byname(pdev, "atu");
13281327
if (IS_ERR(atu_base)) {
13291328
ret = PTR_ERR(atu_base);
13301329
goto err_get_sync;

‎drivers/pci/controller/dwc/pcie-artpec6.c

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -455,8 +455,7 @@ static int artpec6_add_pcie_ep(struct artpec6_pcie *artpec6_pcie,
455455
ep = &pci->ep;
456456
ep->ops = &pcie_ep_ops;
457457

458-
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2");
459-
pci->dbi_base2 = devm_ioremap_resource(dev, res);
458+
pci->dbi_base2 = devm_platform_ioremap_resource_byname(pdev, "dbi2");
460459
if (IS_ERR(pci->dbi_base2))
461460
return PTR_ERR(pci->dbi_base2);
462461

@@ -481,8 +480,6 @@ static int artpec6_pcie_probe(struct platform_device *pdev)
481480
struct device *dev = &pdev->dev;
482481
struct dw_pcie *pci;
483482
struct artpec6_pcie *artpec6_pcie;
484-
struct resource *dbi_base;
485-
struct resource *phy_base;
486483
int ret;
487484
const struct of_device_id *match;
488485
const struct artpec_pcie_of_data *data;
@@ -512,13 +509,12 @@ static int artpec6_pcie_probe(struct platform_device *pdev)
512509
artpec6_pcie->variant = variant;
513510
artpec6_pcie->mode = mode;
514511

515-
dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
516-
pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
512+
pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "dbi");
517513
if (IS_ERR(pci->dbi_base))
518514
return PTR_ERR(pci->dbi_base);
519515

520-
phy_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
521-
artpec6_pcie->phy_base = devm_ioremap_resource(dev, phy_base);
516+
artpec6_pcie->phy_base =
517+
devm_platform_ioremap_resource_byname(pdev, "phy");
522518
if (IS_ERR(artpec6_pcie->phy_base))
523519
return PTR_ERR(artpec6_pcie->phy_base);
524520

‎drivers/pci/controller/dwc/pcie-designware-plat.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -153,8 +153,7 @@ static int dw_plat_add_pcie_ep(struct dw_plat_pcie *dw_plat_pcie,
153153
ep = &pci->ep;
154154
ep->ops = &pcie_ep_ops;
155155

156-
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2");
157-
pci->dbi_base2 = devm_ioremap_resource(dev, res);
156+
pci->dbi_base2 = devm_platform_ioremap_resource_byname(pdev, "dbi2");
158157
if (IS_ERR(pci->dbi_base2))
159158
return PTR_ERR(pci->dbi_base2);
160159

‎drivers/pci/controller/dwc/pcie-hisi.c

Lines changed: 0 additions & 219 deletions
Original file line numberDiff line numberDiff line change
@@ -10,15 +10,10 @@
1010
*/
1111
#include <linux/interrupt.h>
1212
#include <linux/init.h>
13-
#include <linux/mfd/syscon.h>
14-
#include <linux/of_address.h>
15-
#include <linux/of_pci.h>
1613
#include <linux/platform_device.h>
17-
#include <linux/of_device.h>
1814
#include <linux/pci.h>
1915
#include <linux/pci-acpi.h>
2016
#include <linux/pci-ecam.h>
21-
#include <linux/regmap.h>
2217
#include "../../pci.h"
2318

2419
#if defined(CONFIG_PCI_HISI) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
@@ -118,220 +113,6 @@ const struct pci_ecam_ops hisi_pcie_ops = {
118113

119114
#ifdef CONFIG_PCI_HISI
120115

121-
#include "pcie-designware.h"
122-
123-
#define PCIE_SUBCTRL_SYS_STATE4_REG 0x6818
124-
#define PCIE_HIP06_CTRL_OFF 0x1000
125-
#define PCIE_SYS_STATE4 (PCIE_HIP06_CTRL_OFF + 0x31c)
126-
#define PCIE_LTSSM_LINKUP_STATE 0x11
127-
#define PCIE_LTSSM_STATE_MASK 0x3F
128-
129-
#define to_hisi_pcie(x) dev_get_drvdata((x)->dev)
130-
131-
struct hisi_pcie;
132-
133-
struct pcie_soc_ops {
134-
int (*hisi_pcie_link_up)(struct hisi_pcie *hisi_pcie);
135-
};
136-
137-
struct hisi_pcie {
138-
struct dw_pcie *pci;
139-
struct regmap *subctrl;
140-
u32 port_id;
141-
const struct pcie_soc_ops *soc_ops;
142-
};
143-
144-
/* HipXX PCIe host only supports 32-bit config access */
145-
static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
146-
u32 *val)
147-
{
148-
u32 reg;
149-
u32 reg_val;
150-
void *walker = &reg_val;
151-
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
152-
153-
walker += (where & 0x3);
154-
reg = where & ~0x3;
155-
reg_val = dw_pcie_readl_dbi(pci, reg);
156-
157-
if (size == 1)
158-
*val = *(u8 __force *) walker;
159-
else if (size == 2)
160-
*val = *(u16 __force *) walker;
161-
else if (size == 4)
162-
*val = reg_val;
163-
else
164-
return PCIBIOS_BAD_REGISTER_NUMBER;
165-
166-
return PCIBIOS_SUCCESSFUL;
167-
}
168-
169-
/* HipXX PCIe host only supports 32-bit config access */
170-
static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
171-
u32 val)
172-
{
173-
u32 reg_val;
174-
u32 reg;
175-
void *walker = &reg_val;
176-
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
177-
178-
walker += (where & 0x3);
179-
reg = where & ~0x3;
180-
if (size == 4)
181-
dw_pcie_writel_dbi(pci, reg, val);
182-
else if (size == 2) {
183-
reg_val = dw_pcie_readl_dbi(pci, reg);
184-
*(u16 __force *) walker = val;
185-
dw_pcie_writel_dbi(pci, reg, reg_val);
186-
} else if (size == 1) {
187-
reg_val = dw_pcie_readl_dbi(pci, reg);
188-
*(u8 __force *) walker = val;
189-
dw_pcie_writel_dbi(pci, reg, reg_val);
190-
} else
191-
return PCIBIOS_BAD_REGISTER_NUMBER;
192-
193-
return PCIBIOS_SUCCESSFUL;
194-
}
195-
196-
static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie)
197-
{
198-
u32 val;
199-
200-
regmap_read(hisi_pcie->subctrl, PCIE_SUBCTRL_SYS_STATE4_REG +
201-
0x100 * hisi_pcie->port_id, &val);
202-
203-
return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
204-
}
205-
206-
static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
207-
{
208-
struct dw_pcie *pci = hisi_pcie->pci;
209-
u32 val;
210-
211-
val = dw_pcie_readl_dbi(pci, PCIE_SYS_STATE4);
212-
213-
return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
214-
}
215-
216-
static int hisi_pcie_link_up(struct dw_pcie *pci)
217-
{
218-
struct hisi_pcie *hisi_pcie = to_hisi_pcie(pci);
219-
220-
return hisi_pcie->soc_ops->hisi_pcie_link_up(hisi_pcie);
221-
}
222-
223-
static const struct dw_pcie_host_ops hisi_pcie_host_ops = {
224-
.rd_own_conf = hisi_pcie_cfg_read,
225-
.wr_own_conf = hisi_pcie_cfg_write,
226-
};
227-
228-
static int hisi_add_pcie_port(struct hisi_pcie *hisi_pcie,
229-
struct platform_device *pdev)
230-
{
231-
struct dw_pcie *pci = hisi_pcie->pci;
232-
struct pcie_port *pp = &pci->pp;
233-
struct device *dev = &pdev->dev;
234-
int ret;
235-
u32 port_id;
236-
237-
if (of_property_read_u32(dev->of_node, "port-id", &port_id)) {
238-
dev_err(dev, "failed to read port-id\n");
239-
return -EINVAL;
240-
}
241-
if (port_id > 3) {
242-
dev_err(dev, "Invalid port-id: %d\n", port_id);
243-
return -EINVAL;
244-
}
245-
hisi_pcie->port_id = port_id;
246-
247-
pp->ops = &hisi_pcie_host_ops;
248-
249-
ret = dw_pcie_host_init(pp);
250-
if (ret) {
251-
dev_err(dev, "failed to initialize host\n");
252-
return ret;
253-
}
254-
255-
return 0;
256-
}
257-
258-
static const struct dw_pcie_ops dw_pcie_ops = {
259-
.link_up = hisi_pcie_link_up,
260-
};
261-
262-
static int hisi_pcie_probe(struct platform_device *pdev)
263-
{
264-
struct device *dev = &pdev->dev;
265-
struct dw_pcie *pci;
266-
struct hisi_pcie *hisi_pcie;
267-
struct resource *reg;
268-
int ret;
269-
270-
hisi_pcie = devm_kzalloc(dev, sizeof(*hisi_pcie), GFP_KERNEL);
271-
if (!hisi_pcie)
272-
return -ENOMEM;
273-
274-
pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
275-
if (!pci)
276-
return -ENOMEM;
277-
278-
pci->dev = dev;
279-
pci->ops = &dw_pcie_ops;
280-
281-
hisi_pcie->pci = pci;
282-
283-
hisi_pcie->soc_ops = of_device_get_match_data(dev);
284-
285-
hisi_pcie->subctrl =
286-
syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl");
287-
if (IS_ERR(hisi_pcie->subctrl)) {
288-
dev_err(dev, "cannot get subctrl base\n");
289-
return PTR_ERR(hisi_pcie->subctrl);
290-
}
291-
292-
reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi");
293-
pci->dbi_base = devm_pci_remap_cfg_resource(dev, reg);
294-
if (IS_ERR(pci->dbi_base))
295-
return PTR_ERR(pci->dbi_base);
296-
platform_set_drvdata(pdev, hisi_pcie);
297-
298-
ret = hisi_add_pcie_port(hisi_pcie, pdev);
299-
if (ret)
300-
return ret;
301-
302-
return 0;
303-
}
304-
305-
static struct pcie_soc_ops hip05_ops = {
306-
&hisi_pcie_link_up_hip05
307-
};
308-
309-
static struct pcie_soc_ops hip06_ops = {
310-
&hisi_pcie_link_up_hip06
311-
};
312-
313-
static const struct of_device_id hisi_pcie_of_match[] = {
314-
{
315-
.compatible = "hisilicon,hip05-pcie",
316-
.data = (void *) &hip05_ops,
317-
},
318-
{
319-
.compatible = "hisilicon,hip06-pcie",
320-
.data = (void *) &hip06_ops,
321-
},
322-
{},
323-
};
324-
325-
static struct platform_driver hisi_pcie_driver = {
326-
.probe = hisi_pcie_probe,
327-
.driver = {
328-
.name = "hisi-pcie",
329-
.of_match_table = hisi_pcie_of_match,
330-
.suppress_bind_attrs = true,
331-
},
332-
};
333-
builtin_platform_driver(hisi_pcie_driver);
334-
335116
static int hisi_pcie_platform_init(struct pci_config_window *cfg)
336117
{
337118
struct device *dev = cfg->parent;

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