Skip to content

Commit 2b50e49

Browse files
Sowjanya Komatinenithierryreding
Sowjanya Komatineni
authored and
thierryreding
committed
clk: tegra: Add Tegra OSC to clock lookup
OSC is one of the parent for Tegra PMC clocks clk_out_1, clk_out_2, and clk_out_3. This patch adds Tegra OSC to clock lookup. Tested-by: Dmitry Osipenko <[email protected]> Reviewed-by: Dmitry Osipenko <[email protected]> Signed-off-by: Sowjanya Komatineni <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
1 parent 9a85eb4 commit 2b50e49

File tree

6 files changed

+14
-0
lines changed

6 files changed

+14
-0
lines changed

‎drivers/clk/tegra/clk-id.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,7 @@ enum clk_id {
4646
tegra_clk_clk_m,
4747
tegra_clk_clk_m_div2,
4848
tegra_clk_clk_m_div4,
49+
tegra_clk_osc,
4950
tegra_clk_osc_div2,
5051
tegra_clk_osc_div4,
5152
tegra_clk_clk_out_1,

‎drivers/clk/tegra/clk-tegra-fixed.c

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,12 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
4646
return -EINVAL;
4747
}
4848

49+
dt_clk = tegra_lookup_dt_id(tegra_clk_osc, clks);
50+
if (!dt_clk)
51+
return 0;
52+
4953
osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq);
54+
*dt_clk = osc;
5055

5156
/* osc_div2 */
5257
dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div2, clks);

‎drivers/clk/tegra/clk-tegra114.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -737,6 +737,7 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
737737
[tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
738738
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
739739
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
740+
[tegra_clk_osc] = { .dt_id = TEGRA114_CLK_OSC, .present = true },
740741
[tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true },
741742
[tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true },
742743
[tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
@@ -819,6 +820,7 @@ static struct tegra_devclk devclks[] __initdata = {
819820
{ .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
820821
{ .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
821822
{ .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
823+
{ .con_id = "osc", .dt_id = TEGRA114_CLK_OSC },
822824
{ .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 },
823825
{ .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 },
824826
{ .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },

‎drivers/clk/tegra/clk-tegra124.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -862,6 +862,7 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
862862
[tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
863863
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },
864864
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },
865+
[tegra_clk_osc] = { .dt_id = TEGRA124_CLK_OSC, .present = true },
865866
[tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true },
866867
[tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true },
867868
[tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
@@ -945,6 +946,7 @@ static struct tegra_devclk devclks[] __initdata = {
945946
{ .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
946947
{ .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
947948
{ .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },
949+
{ .con_id = "osc", .dt_id = TEGRA124_CLK_OSC },
948950
{ .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 },
949951
{ .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 },
950952
{ .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },

‎drivers/clk/tegra/clk-tegra210.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2373,6 +2373,7 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
23732373
[tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },
23742374
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true },
23752375
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true },
2376+
[tegra_clk_osc] = { .dt_id = TEGRA210_CLK_OSC, .present = true },
23762377
[tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true },
23772378
[tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true },
23782379
[tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },
@@ -2501,6 +2502,7 @@ static struct tegra_devclk devclks[] __initdata = {
25012502
{ .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
25022503
{ .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },
25032504
{ .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },
2505+
{ .con_id = "osc", .dt_id = TEGRA210_CLK_OSC },
25042506
{ .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 },
25052507
{ .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 },
25062508
{ .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },

‎drivers/clk/tegra/clk-tegra30.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -583,6 +583,7 @@ static struct tegra_devclk devclks[] __initdata = {
583583
{ .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
584584
{ .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 },
585585
{ .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 },
586+
{ .con_id = "osc", .dt_id = TEGRA30_CLK_OSC },
586587
{ .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 },
587588
{ .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 },
588589
{ .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
@@ -687,6 +688,7 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
687688
[tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
688689
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true },
689690
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true },
691+
[tegra_clk_osc] = { .dt_id = TEGRA30_CLK_OSC, .present = true },
690692
[tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true },
691693
[tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true },
692694
[tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },

0 commit comments

Comments
 (0)